System and Peripheral Control Registers
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SPNU563A–March 2018
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Architecture
NOTE: Non-implemented clock sources should not be enabled or used. A list of the available clock
sources is shown in the Table 2-29.
2.5.1.17 Peripheral Asynchronous Clock Source Register (VCLKASRC)
The VCLKASRC register, shown in Figure 2-24 and described in Table 2-36, sets the clock source for the
asynchronous peripheral clock domains to be configured to run from a specific clock source.
Figure 2-24. Peripheral Asynchronous Clock Source Register (VCLKASRC) (offset = 4Ch)
31 28 27 24 23 20 19 16
Reserved Reserved Reserved Reserved
R-0 R/WP-1h R-0 R/WP-1h
15 12 11 8 7 4 3 0
Reserved VCLKA2S Reserved VCLKA1S
R-0 R/WP-9h R-0 R/WP-9h
LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset
Table 2-36. Peripheral Asynchronous Clock Source Register (VCLKASRC) Field Descriptions
Bit Field Value Description
31-28 Reserved 0 Reads return 0. Writes have no effect.
27-24 Reserved 0-1 Reads return 0 or 1 and privilege mode writes allowed.
23-20 Reserved 0 Reads return 0. Writes have no effect.
19-16 Reserved 0-1 Reads return 0 or 1 and privilege mode writes allowed.
15-12 Reserved 0 Reads return 0. Writes have no effect.
11-8 VCLKA2S Peripheral asynchronous clock2 source.
0 Clock source0 is the source for peripheral asynchronous clock2.
1h Clock source1 is the source for peripheral asynchronous clock2.
2h Clock source2 is the source for peripheral asynchronous clock2.
3h Clock source3 is the source for peripheral asynchronous clock2.
4h Clock source4 is the source for peripheral asynchronous clock2.
5h Clock source5 is the source for peripheral asynchronous clock2.
6h Clock source6 is the source for peripheral asynchronous clock2.
7h Clock source7 is the source for peripheral asynchronous clock2.
8h-Fh VCLK is the source for peripheral asynchronous clock2.
7-4 Reserved 0 Reads return 0. Writes have no effect.
3-0 VCLKA1S Peripheral asynchronous clock1 source.
0 Clock source0 is the source for peripheral asynchronous clock1.
1h Clock source1 is the source for peripheral asynchronous clock1.
2h Clock source2 is the source for peripheral asynchronous clock1.
3h Clock source3 is the source for peripheral asynchronous clock1.
4h Clock source4 is the source for peripheral asynchronous clock1.
5h Clock source5 is the source for peripheral asynchronous clock1.
6h Clock source6 is the source for peripheral asynchronous clock1.
7h Clock source7 is the source for peripheral asynchronous clock1.
8h-Fh VCLK is the source for peripheral asynchronous clock1.
NOTE: Non-implemented clock sources should not be enabled or used. A list of the available clock
sources is shown in Table 2-29.
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