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System and Peripheral Control Registers
157
SPNU563A–March 2018
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Architecture
2.5.1.9 SYS Pin Control Register 9 (SYSPC9)
The SYSPC9 register, shown in Figure 2-16 and described in Table 2-27, controls the pull up/pull down
configuration of the ECLK pin when it is configured as an input in GIO mode.
Figure 2-16. SYS Pin Control Register 9 (SYSPC9) (offset = 20h)
31 16
Reserved
R-0
15 1 0
Reserved ECPCLKPS
R-0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 2-27. SYS Pin Control Register 9 (SYSPC9) Field Descriptions
Bit Field Value Description
31-1 Reserved 0 Reads return 0. Writes have no effect.
0 ECPCLKPS ECLK pull up/pull down select. This bit is only active when ECLK is configured as an input in
GIO mode and the pull up/pull down logic is enabled.
0 ECLK pull down is selected, when pull up/pull down logic is enabled.
1 ECLK pull up is selected, when pull up/pull down logic is enabled.
Note: The ECLK pin pull up/pull down logic is enabled by clearing the ECPCLKPUE bit to
0 in the SYSPC8 register.
Note: The ECLK pin is placed into GIO mode by clearing the ECPCLKFUN bit to 0 in the
SYSPC1 register. The ECLK pin is placed in input mode by clearing the ECPCLKDIR bit
to 0 in the SYSPC2 register.
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