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System and Peripheral Control Registers
155
SPNU563A–March 2018
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Architecture
2.5.1.5 SYS Pin Control Register 5 (SYSPC5)
The SYSPC5 register, shown in Figure 2-12 and described in Table 2-23, controls the set function of the
ECLK pin when it is configured as an output in GIO mode.
Figure 2-12. SYS Pin Control Register 5 (SYSPC5) (offset = 10h)
31 16
Reserved
R-0
15 1 0
Reserved ECPCLKSET
R-0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 2-23. SYS Pin Control Register 5 (SYSPC5) Field Descriptions
Bit Field Value Description
31-1 Reserved 0 Reads return 0. Writes have no effect.
0 ECPCLKSET ECLK data out set. This bit drives the output of the ECLK pin high when set in GIO output
mode.
0 Write: Writing a 0 has no effect.
1 Write: The ECLK pin is driven to logic high (1).
Note: The current logic state of the ECPCLKDOUT bit will also be displayed by this bit
when the pin is configured in GIO output mode.
Note: The ECLK pin is placed into GIO mode by clearing the ECPCLKFUN bit to 0 in the
SYSPC1 register. The ECLK pin is placed in output mode by setting the ECPCLKDIR bit
to 1 in the SYSPC2 register.
2.5.1.6 SYS Pin Control Register 6 (SYSPC6)
The SYSPC6 register, shown in Figure 2-13 and described in Table 2-24, controls the clear function of the
ECLK pin when it is configured as an output in GIO mode..
Figure 2-13. SYS Pin Control Register 6 (SYSPC6) (offset = 14h)
31 16
Reserved
R-0
15 1 0
Reserved ECPCLKCLR
R-0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 2-24. SYS Pin Control Register 6 (SYSPC6) Field Descriptions
Bit Field Value Description
31-1 Reserved 0 Reads return 0. Writes have no effect.
0 ECPCLKCLR ECLK data out clear. This bit drives the output of the ECLK pin low when set in GIO output
mode.
0 Write: The ECLK pin value is unchanged.
1 Write: The ECLK pin is driven to logic low (0).
Note: The current logic state of the ECPCLKDOUT bit will also be displayed by this bit
when the pin is configured in GIO output mode.
Note: The ECLK pin is placed into GIO mode by clearing the ECPCLKFUN bit to 0 in the
SYSPC1 register. The ECLK pin is placed in output mode by setting the ECPCLKDIR bit
to 1 in the SYSPC2 register.