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System and Peripheral Control Registers
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SPNU563A–March 2018
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Architecture
2.5.1.22 MBIST Controller/ Memory Initialization Enable Register (MSINENA)
The MSINENA register, shown in Figure 2-29 and described in Table 2-41, enables PBIST controllers for
memory self test and the memory modules initialized during automatic hardware memory initialization.
Figure 2-29. MBIST Controller/Memory Initialization Enable Register (MSINENA) (offset = 60h)
31 16
MSIENA
R/WP-0
15 0
MSIENA
R/WP-0
LEGEND: R/W = Read/Write; WP = Write in privileged mode only; -n = value after reset
Table 2-41. MBIST Controller/Memory Initialization Enable Register (MSINENA) Field Descriptions
Bit Field Value Description
31-0 MSIENA PBIST controller and memory initialization enable register. In memory self-test mode, all the
corresponding bits of the memories to be tested should be set before enabling the global memory self-
test controller key (MSTGENA) in the MSTGCR register (offset 58h). The reason for this is that
MSTGENA, in addition to being the global enable for all individual PBIST controllers, is the source for
the reset generation to all the PBIST controller state machines. Disabling the MSTGENA or
MINITGENA key (by writing from an Ah to any other value) will reset all the MSIENA[31-0] bits to their
default values.
0 In memory self-test mode (MSTGENA = Ah):
PBIST controller [31-0] is disabled.
In memory Initialization mode (MINITGENA = Ah):
Memory module [31-0] auto hardware initialization is disabled.
1 In memory self-test mode (MSTGENA = Ah):
PBIST controller [31-0] is enabled.
In memory Initialization mode (MINITGENA = Ah):
Memory module [31-0] auto hardware initialization is enabled.
Note: Software should ensure that both the memory self-test global enable key (MSTGENA) and
the memory hardware initialization global key (MINITGENA) are not enabled at the same time.
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