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1E C P D I V
NV C L K o r O S C I
E C L K
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System and Peripheral Control Registers
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SPNU563A–March 2018
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Architecture
2.5.2.3 ECP Control Register 1 (ECPCNTL1)
The ECP register, shown in Figure 2-61 and described in Table 2-74, configures the ECLK2 pin in
functional mode.
NOTE: ECLK2 Functional mode configuration.
The ECLK2 pin must be placed into Functional mode by setting the ECPCLKFUN bit to 1 in
the SYSPC1 register before a clock source will be visible on the ECLK pin.
Figure 2-61. ECP Control Register 1 (ECPCNTL1) (offset = 28h)
31 28 27 25 24 23 22 16
ECP_KEY Reserved ECPSSEL ECPCOS Reserved
R/WP-5h R-0 R/W-0 R/W-0 R-0
15 0
ECPDIV
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 2-74. ECP Control Register 1 (ECPCNTL1) Field Descriptions
Bit Field Value Description
31-28 ECP_KEY Enable ECP clock logic for ECLK2.
Ah Clock functionality of ECP clock is enabled.
Others Clock functionality of ECP clock is disabled.
27-25 Reserved 0 Reads return 0. Writes have no effect.
24 ECPSSEL This bit allows the selection between VCLK and OSCIN as the clock source for ECLK2.
0 VCLK is selected as the ECP clock source.
1 OSCIN is selected as the ECP clock source.
23 ECPCOS ECP continue on suspend.
Note: Suspend mode is entered while performing certain JTAG debugging operations.
0 ECLK output is disabled in suspend mode. ECLK output will be shut off and will not be seen on
the I/O pin of the device.
1 ECLK output is not disabled in suspend mode. ECLK output will not be shut off and will be seen
on the I/O pin of the device.
22-16 Reserved 0 Reads return 0. Writes have no effect.
15-0 ECPDIV 0-FFFFh ECP divider value. The value of ECPDIV bits determine the external clock (ECP clock) frequency
as a ratio of VBUS clock or OSCIN as shown in the formula:
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