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System and Peripheral Control Registers
207
SPNU563A–March 2018
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Architecture
2.5.2.2 CPU Logic Bist Clock Divider (STCLKDIV)
This register is shown in Figure 2-60 and described in Table 2-73.
Figure 2-60. CPU Logic BIST Clock Prescaler (STCLKDIV) (offset = 08h)
31 27 26 24 23 16
Reserved CLKDIV Reserved
R-0 R/WP-0 R-0
15 0
Reserved
R-0
LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset
Table 2-73. CPU Logic BIST Clock Prescaler (STCLKDIV) Field Descriptions
Bit Field Value Description
31-27 Reserved 0 Reads return 0. Writes have no effect.
26-24 CLKDIV 0 Clock divider/prescaler for CPU clock during logic BIST
23-0 Reserved 0 Reads return 0. Writes have no effect.
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