System and Peripheral Control Registers
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SPNU563A–March 2018
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Architecture
2.5.2.1 PLL Control Register 3 (PLLCTL3)
The PLLCTL3 register is shown in Figure 2-59 and described in Table 2-72; controls the settings of PLL2
(Clock Source 6 - FPLL).
Figure 2-59. PLL Control Register 3 (PLLCTL3) (offset = 00h)
31 29 28 24 23 22 21 16
ODPLL2 PLLDIV2 Reserved REFCLKDIV2
R/WP-0 R/WP-4h R-0 R/WP-0
15 0
PLLMUL2
R/WP-1300h
LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset
Table 2-72. PLL Control Register 3 (PLLCTL3) Field Descriptions
Bit Field Value Description
31-29 ODPLL2 Internal PLL Output Divider
OD2 = ODPLL2 + 1, ranges from 1 to 8.
f
post_ODCLK2
= f
output_CLK2 / OD2
Note: PLL output clock is gated off if ODPLL2 is changed while the PLL#2 is active.
0 f
post_ODCLK2
= f
output_CLK2 / 1
1h f
post_ODCLK2
= f
output_CLK2 / 2
: :
7h f
post_ODCLK2
= f
output_CLK2 / 8
28-24 PLLDIV2 PLL2 Output Clock Divider
R2 = PLLDIV2 + 1, ranges from 1 to 32.
f
PLL2 CLK
= f
post_ODCLK2
/ R2
0 f
PLL2 CLK
= f
post_ODCLK2
/ 1
1h f
PLL2 CLK
= f
post_ODCLK2
/ 2
: :
1Fh f
PLL2 CLK
= f
post_ODCLK2
/ 32
23-22 Reserved 0 Value has no effect on PLL operation.
21-16 REFCLKDIV2 Reference Clock Divider
NR2 = REFCLKDIV2 + 1, ranges from 1 to 64.
f
INTCLK2
= f
OSCIN
/ NR2
Note: This value should not be changed while the PLL2 is active.
0 f
INTCLK2
= f
OSCIN
/ 1
1h f
INTCLK2
= f
OSCIN
/ 2
: :
3Fh f
INTCLK2
= f
OSCIN
/ 64
15-0 PLLMUL2 PLL2 Multiplication Factor
NF2 = (PLLMUL2 / 256) + 1, valid multiplication factors are from 1 to 256.
f
VCOCLK2
= f
INTCLK2
x NF2
User and privileged mode (read):
Privileged mode (write):
100h f
VCOCLK2
= f
INTCLK2
x 1
: :
5B00h f
VCOCLK2
= f
INTCLK2
x 92
5C00h f
VCOCLK2
= f
INTCLK2
x 93
: :
FF00h f
VCOCLK2
= f
INTCLK2
x 256
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