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System and Peripheral Control Registers
213
SPNU563A–March 2018
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Architecture
2.5.2.8 IP ECC Error Enable Register (IP1ECCERREN)
This register is shown in Figure 2-66 and described in Table 2-79.
Figure 2-66. IP ECC Error Enable Register (IP1ECCERREN) (offset = 78h)
31 28 27 24 23 20 19 16
Reserved Reserved Reserved Reserved
R-0 R/WP-5h R/WP-5h
15 12 11 8 7 4 3 0
Reserved IP2_ECC_KEY Reserved IP1_ECC_KEY
R-0 R/WP-5h R-0 R/WP-5h
LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset
Table 2-79. Clock Slip Register (CLKSLIP) Field Descriptions
Bit Field Value Description
31-28 Reserved 0 Reads return 0. Writes have no effect.
27-24 Reserved 0-Fh Reads return 0 or 1 and depends on what is written in privileged mode. The
functionality of this bit is unavailable in this device.
23-20 Reserved 0 Reads return 0. Writes have no effect.
19-16 Reserved 0-Fh Reads return 0 or 1 and depends on what is written in privileged mode. The
functionality of this bit is unavailable in this device.
15-12 Reserved 0 Reads return 0. Writes have no effect.
11-8 IP2_ECC_KEY ECC Error Enable Key for PS_SCR_M master. There is an ECC Evaluation block
inside the CPU Interconnect Subsystem responsible for ECC correction and detection
on the data path for transactions initiated by the PS_SCR_M master. If an ECC error
(either single-bit or double-bit error) is detected, then the corresponding error signal is
asserted if ECC enable key written to IP2_ECC_KEY is Ah.
Others Disable ECC error generation for ECC errors detected on PS_SCR_M master by the
CPU Interconnect Subsystem.
Ah Enable ECC error generation for ECC errors detected on PS_SCR_M master by the
CPU Interconnect Subsystem.
7-4 Reserved 0 Reads return 0. Writes have no effect.
3-0 IP1_ECC_KEY ECC Error Enable Key for DMA Port A master. There is an ECC Evaluation block
inside the CPU Interconnect Subsystem responsible for ECC correction and detection
on the data path for transactions initiated by the DMA Port A master. If an ECC error
(either single-bit or double-bit error) is detected, then the corresponding error signal is
asserted if ECC enable key written to IP1_ECC_KEY is Ah.
Others Disable ECC error generation for ECC errors detected on DMA Port A master by the
CPU Interconnect Subsystem.
Ah Enable ECC error generation for ECC errors detected on DMA Port A master by the
CPU Interconnect Subsystem.
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