Texas Instruments TMS570LC4357 User Manual

System and Peripheral Control Registers www.ti.com
210
SPNU563A–March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated
Architecture
2.5.2.5 Peripheral Asynchronous Clock Configuration 1 Register (VCLKACON1)
This register is shown in Figure 2-63 and described in Table 2-76.
Figure 2-63. Peripheral Asynchronous Clock Configuration 1 Register (VCLKACON1) [offset = 40h]
31 27 26 24
Reserved VCLKA4R
R-0 R/WP-1h
23 21 20 19 16
Reserved VCLKA4_DIV_
CDDIS
VCLKA4S
R-0 R/WP-0 R/WP-9h
15 11 10 8 7 5 4 0
Reserved Reserved Reserved Reserved
R-0 R/WP-1h R-0 R/WP-9h
LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset
Table 2-76. Peripheral Asynchronous Clock Configuration 1 Register (VCLKACON1)
Field Descriptions
Bit Field Value Description
31-27 Reserved 0 Reads return 0. Writes have no effect.
26-24 VCLKA4R Clock divider for the VCLKA4 source. Output will be present on VCLKA4_DIVR.
VCLKA4 domain will be enabled by writing to the CDDIS register and VCLKA4_DIV_CDDIS bit.
It can inferred that VCLKA4_DIV clock is disabled when VCLKA4 clock is disabled.
0 The ratio is VCLKA4 divided by 1.
: :
7h The ratio is VCLKA4 divided by 8.
23-21 Reserved 0 Reads return 0. Writes have no effect.
20 VCLKA4_DIV_CDDIS Disable the VCLKA4 divider output.
VCLKA4 domain will be enabled by writing to the CDDIS register.
0 Enable the prescaled VCLKA4 clock on VCLKA4_DIVR.
1 Disable the prescaled VCLKA4 clock on VCLKA4_DIVR.
19-16 VCLKA4S Peripheral asynchronous clock4 source.
0 Clock source0 is the source for peripheral asynchronous clock4.
1h Clock source1 is the source for peripheral asynchronous clock4.
2h Clock source2 is the source for peripheral asynchronous clock4.
3h Clock source3 is the source for peripheral asynchronous clock4.
4h Clock source4 is the source for peripheral asynchronous clock4.
5h Clock source5 is the source for peripheral asynchronous clock4.
6h Clock source6 is the source for peripheral asynchronous clock4.
7h Clock source7 is the source for peripheral asynchronous clock4.
8h-Fh VCLK or a divided VCLK is the source for peripheral asynchronous clock4. See the device-
specific data manual for details.
15-0 Reserved 109h Reserved
NOTE: Non-implemented clock sources should not be enabled or used. A list of the available clock
sources is shown in the Table 2-29.

Texas Instruments TMS570LC4357 Specifications

General

Brand	Texas Instruments
Model	TMS570LC4357
Category	Microcontrollers
Language	English