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Control Registers and Control Packets
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SPNU563A–March 2018
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Direct Memory Access Controller (DMA) Module
20.3.1.2 Channel Pending Register (PEND)
Figure 20-20. Channel Pending Register (PEND) [offset = 04h]
31 0
PEND[31:0]
R-0
LEGEND: R = Read only; -n = value after reset
Table 20-10. Channel Pending Register (PEND) Field Descriptions
Bit Field Value Description
31-0 PEND[n] Channel pending register. Bit 0 corresponds to channel 0, bit 1 corresponds to channel 1, and so on.
Reading from PEND gives the channel pending information no matter if the channel was initiated by SW
or HW. Once set, it remains set even if the corresponding channel is disabled via HWCHENA or
SWCHENA. The pending bit is automatically cleared for the following conditions:
• At the end of a frame or a block transfer depending on how the channel is triggered as programmed
in the TTYPE bit field of CHCTRL.
• The control packet is modified after the pending bit is set.
• A bus error occurs.
• A transaction parity error occurs
0 The corresponding channel is inactive.
1 The corresponding channel is pending and is waiting for service.
20.3.1.3 DMA Status Register (DMASTAT)
Figure 20-21. DMA Status Register (DMASTAT) [offset = 0Ch]
31 0
STCH[31:0]
R-0
LEGEND: R = Read only; -n = value after reset
Table 20-11. DMA Status Register (DMASTAT) Field Descriptions
Bit Field Value Description
31-0 STCH[n] Status of DMA channels. Bit 0 corresponds to channel 0, bit 1 corresponds to channel 1, and so on.
0 The channel is not being currently processed.
1 The channel is currently being processed using one of the FIFOs.
Note: The status of a channel currently being processed remains active even if emulation mode is
entered or DMA is disabled via DMA_EN bit. Since there are two FIFOs, up to 2 bits can be set in this
register at any given time.
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