Memory Organization
www.ti.com
136
SPNU563A–March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated
Architecture
Table 2-6 maps the different algorithms supported in application mode for the RAM groups. The table also
lists the background pattern options available for each algorithm.
Table 2-6. PBIST Algorithm Mapping
Sr. No.
ALGO
Register
Value Algorithm
Memories
Under
Test
Available
Background
Patterns Valid RAM Groups
Valid
RINFOL/RINFOU
Register Value
1 0x00000001 triple_read_slow_read ROM 1,2,3,4 0x0000000F/
0x00000000
2 0x00000002 triple_read_fast_read ROM 1,2,3,4 0x0000000F/
0x00000000
3 0x00000004 march13n Two-port 0x00000000,
0x96699669,
0x0F0F0F0F,
0xAA55AA55,
0xC3C3C3C3
5,6,7,8,9,10,11,12,13
,
14,16,17,18,19,20,21
,
22,23,24,25,26,27,28
0x0FFFBFF0/
0x00000000
4 0x00000008 march13n Single-port 0x00000000,
0x96699669,
0x0F0F0F0F,
0xAA55AA55,
0xC3C3C3C3
29,30,31,32,35,36,37 0xF0000000/
0x0000001C
NOTE: Recommended Memory Test Algorithm
March13 is the most recommended algorithm for the memory self-test.
For GCLK1 = 300 MHz, HCLK = 150 MHz, VCLK = 75 MHz, PBIST ROM_CLK = 75 MHz, the March13
algorithm takes about 29.08 ms to run on all on-chip SRAMs.
NOTE: PBIST ROM_CLK can be prescaled from GCLK1 via ROM_DIV bits of the MSTGCR
register. The valid ratio is either /1, /2 or /4 or /8. See Section 2.5.1.20 for detail. Maximum
PBIST ROM_CLK frequency supported is 82.5MHz.
To Next Page
Loading...
Need help?
General
