Control Registers and Control Packets
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SPNU563A–March 2018
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Direct Memory Access Controller (DMA) Module
20.3.1.7 SW Channel Enable Set and Status Register (SWCHENAS)
Figure 20-25. SW Channel Enable Set and Status Register (SWCHENAS) [offset = 24h]
31 0
SWCHENA[31:0]
R/WP-0
LEGEND: R/W = Read/Write; WP = Write in privilege mode only; -n = value after reset
Table 20-15. SW Channel Enable Set and Status Register (SWCHENAS) Field Descriptions
Bit Field Value Description
31-0 SWCHENA[n] SW channel enable bit. Bit 0 corresponds to channel 0, bit 1 corresponds to channel 1, and so on.
Writing a 1 to a bit triggers a SW request on the corresponding channel to start a DMA transaction.
The corresponding bit is automatically cleared by the following conditions.
• The corresponding bit is cleared after one frame transfer if the TTYPE bit in Channel Control
Register (CHCTRL) is programmed for frame transfer.
• The corresponding bit is cleared after one block transfer if the corresponding TTYPE bit is
programmed for block transfer and the auto-initiation bit is not enabled.
• The control packet is modified after the pending bit is set.
• The corresponding bit is cleared after one block transfer when TTYPE bit is programmed for
blocks transfer and if the corresponding bit in HW channel enable register (HWCHENAS) is
enabled. When a channel is enabled for both HW and SW, the state machine will initiate
transfers based on the SW first. After one block transfer is complete, the corresponding bit in the
SWCHENA register is then cleared. The same channel is serviced again by a HW DMA request.
• The corresponding bit is cleared if a bus error is detected.
• A transaction parity error occurs.
Reading from SWCHENAS gives the status (enabled/disabled) of channels 0 through 31.
0 The corresponding channel is not triggered by SW request.
1 The corresponding channel is triggered by SW request.
20.3.1.8 SW Channel Enable Reset and Status Register (SWCHENAR)
Figure 20-26. SW Channel Enable Reset and Status Register (SWCHENAR) [offset = 2Ch]
31 0
SWCHDIS[31:0]
R/WP-0
LEGEND: R/W = Read/Write; WP = Write in privilege mode only; -n = value after reset
Table 20-16. SW Channel Enable Reset and Status Register (SWCHENAR) Field Descriptions
Bit Field Value Description
31-0 SWCHDIS[n] SW channel disable bit. Bit 0 corresponds to channel 0, bit 1 corresponds to channel 1, and so on.
0 Read: The corresponding channel was not triggered by SW.
Write: No effect.
1 Read: The corresponding channel was triggered by SW.
Write: The corresponding channel is disabled.
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