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Control Registers and Control Packets
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SPNU563A–March 2018
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Direct Memory Access Controller (DMA) Module
20.3.1.9 Channel Priority Set Register (CHPRIOS)
Figure 20-27. Channel Priority Set Register (CHPRIOS) [offset = 34h]
31 0
CPS[31:0]
R/WP-0
LEGEND: R/W = Read/Write; WP = Write in privilege mode only; -n = value after reset
Table 20-17. Channel Priority Set Register (CHPRIOS) Field Descriptions
Bit Field Value Description
31-0 CPS[n] Channel priority set bit. Bit 0 corresponds to channel 0, bit 1 corresponds to channel 1, and so on.
Writing a 1 to a bit assigns the corresponding channel to the high priority queue.
0 Read: The corresponding channel is assigned to the low priority queue.
Write: No effect.
1 Read and write: The corresponding channel is assigned to high priority queue.
20.3.1.10 Channel Priority Reset Register (CHPRIOR)
Figure 20-28. Channel Priority Reset Register (CHPRIOR) [offset = 3Ch]
31 0
CPR[31:0]
R/WP-0
LEGEND: R/W = Read/Write; WP = Write in privilege mode only; -n = value after reset
Table 20-18. Channel Priority Reset Register (CHPRIOR) Field Descriptions
Bit Field Value Description
31-0 CPR[n] Channel priority reset bit. Bit 0 corresponds to channel 0, bit 1 corresponds to channel 1, and so on.
Writing a 1 to a bit assigns the according channel to the low priority queue.
0 Read: The corresponding channel is assigned to the low priority queue.
Write: No effect.
1 Read: The corresponding channel is assigned to the high priority queue.
Write: The corresponding channel is assigned to the low priority queue.
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