EMIF Module Architecture
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SPNU563A–March 2018
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External Memory Interface (EMIF)
4. Program SDCR to match the characteristics of the attached SDRAM device. This will cause the auto-
initialization sequence in Section 21.2.5.4 to be re-run with the new value of RR.
5. Perform a read from the SDRAM to assure that step 5 of this procedure will occur after the initialization
process has completed. Alternatively, wait for 200 μs instead of performing a read.
6. Finally, program the RR field to match that of the attached device's refresh interval. See
Section 21.2.5.6.1 details on determining the appropriate value.
After following the above procedure, the EMIF is ready to perform accesses to the attached SDRAM
device. See Section 21.4 for an example of configuring the SDRAM interface.
21.2.5.6 EMIF Refresh Controller
An SDRAM device requires that each of its rows be refreshed at a minimum required rate. The EMIF can
meet this constraint by performing auto refresh cycles at or above this required rate. An auto refresh cycle
consists of issuing a PRE command to all banks of the SDRAM device followed by issuing a REFR
command. To inform the EMIF of the required rate for performing auto refresh cycles, the RR field of the
SDRAM refresh control register (SDRCR) must be programmed. The EMIF will use this value along with
two internal counters to automatically perform auto refresh cycles at the required rate. The auto refresh
cycles cannot be disabled, even if the EMIF is not interfaced with an SDRAM. The remainder of this
section details the EMIF's refresh scheme and provides an example for determining the appropriate value
to place in the RR field of SDRCR.
The two counters used to perform auto-refresh cycles are a 13-bit refresh interval counter and a 4-bit
refresh backlog counter. At reset and upon writing to the RR field, the refresh interval counter is loaded
with the value from RR field and begins decrementing, by one, each EMIF clock cycle. When the refresh
interval counter reaches zero, the following actions occur:
• The refresh interval counter is reloaded with the value from the RR field and restarts decrementing.
• The 4-bit refresh backlog counter increments unless it has already reached its maximum value.
The refresh backlog counter records the number of auto refresh cycles that the EMIF currently has
outstanding. This counter is decremented by one each time an auto refresh cycle is performed and
incremented by one each time the refresh interval counter expires. The refresh backlog counter saturates
at the values of 0000b and 1111b. The EMIF uses the refresh backlog counter to determine the urgency
with which an auto refresh cycle should be performed. The four levels of urgency are described in
Table 21-12. This refresh scheme allows the required refreshes to be performed with minimal impact on
access requests.
Table 21-12. Refresh Urgency Levels
Urgency Level
Refresh Backlog
Counter Range Action Taken
Refresh May 1-3 An auto-refresh cycle is performed only if the EMIF has no requests pending and none
of the SDRAM banks are open.
Refresh Release 4-7 An auto-refresh cycle is performed if the EMIF has no requests pending, regardless of
whether any SDRAM banks are open.
Refresh Need 8-11 An auto-refresh cycle is performed at the completion of the current access unless
there are read requests pending.
Refresh Must 12-15 Multiple auto-refresh cycles are performed at the completion of the current access
until the Refresh Release urgency level is reached. At that point, the EMIF can begin
servicing any new read or write requests.
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