EMIF Module Architecture
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SPNU563A–March 2018
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External Memory Interface (EMIF)
Table 21-9. Description of the SDRAM Timing Register (SDTIMR)
Parameter Description
T_RFC SDRAM Timing Parameters. These fields configure the EMIF to comply with the AC timing
requirements of the attached SDRAM devices. This allows the EMIF to avoid violating SDRAM timing
constraints and to more efficiently schedule its operations. More details about each of these parameters
can be found in the register description in Section 21.3.6. These parameters should be set to satisfy the
corresponding timing requirements found in the SDRAM's datasheet.
T_RP
T_RCD
T_WR
T_RAS
T_RC
T_RRD
Table 21-10. Description of the SDRAM Self Refresh Exit Timing Register (SDSRETR)
Parameter Description
T_XS Self Refresh Exit Parameter. The T_XS field of this register informs the EMIF about the minimum
number of EMIF_CLK cycles required between exiting Self Refresh and issuing any command. This
parameter should be set to satisfy the t
XSR
value for the attached SDRAM device.
21.2.5.4 SDRAM Auto-Initialization Sequence
The EMIF automatically performs an SDRAM initialization sequence, regardless of whether it is interfaced
to an SDRAM device, when either of the following two events occur:
• The EMIF comes out of reset. No memory accesses to the SDRAM and Asynchronous interfaces are
performed until this auto-initialization is complete.
• A write is performed to any of the three least significant bytes of the SDRAM configuration register
(SDCR)
An SDRAM initialization sequence consists of the following steps:
1. If the initialization sequence is activated by a write to SDCR, and if any of the SDRAM banks are open,
the EMIF issues a PRE command with EMIF_A[10] held high to indicate all banks. This is done so that
the maximum ACTV to PRE timing for an SDRAM is not violated.
2. The EMIF drives EMIF_CKE high and begins continuously issuing NOP commands until eight SDRAM
refresh intervals have elapsed. An SDRAM refresh interval is equal to the value of the RR field of
SDRAM refresh control register (SDRCR), divided by the frequency of EMIF_CLK (RR/f
EMIF_CLK
). This
step is used to avoid violating the Power-up constraint of most SDRAM devices that requires 200 μs
(sometimes 100 μs) between receiving stable Vdd and CLK and the issuing of a PRE command.
Depending on the frequency of EMIF_CLK, this step may or may not be sufficient to avoid violating the
SDRAM constraint. See Section 21.2.5.5 for more information.
3. After the refresh intervals have elapsed, the EMIF issues a PRE command with EMIF_A[10] held high
to indicate all banks.
4. The EMIF issues eight AUTO REFRESH commands.
5. The EMIF issues the LMR command with the EMIF_A[9:0] pins set as described in Table 21-11.
6. Finally, the EMIF performs a refresh cycle, which consists of the following steps:
a. Issuing a PRE command with EMIF_A[10] held high if any banks are open
b. Issuing an REF command
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