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RTI Control Registers
603
SPNU563A–March 2018
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Real-Time Interrupt (RTI) Module
17.3.11 RTI Up Counter 1 Register (RTIUC1)
The up counter 1 register holds the current value of the prescale counter 1. This register is shown in
Figure 17-22 and described in Table 17-12.
Figure 17-22. RTI Up Counter 1 Register (RTIUC1) [offset = 34h]
31 16
UC1
R/WP-0
15 0
UC1
R/WP-0
LEGEND: R/W = Read/Write; WP = Write in privileged mode only; -n = value after reset
Table 17-12. RTI Up Counter 1 Register (RTIUC1) Field Descriptions
Bit Field Value Description
31-0 UC1 0-FFFF FFFFh Up counter 1. This register holds the current value of the up counter 1 and prescales the RTI
clock. It will be only updated by a previous read of free running counter 1 (RTIFRC1). This
method of updating effectively gives a 64-bit read of both counters, without having the problem
of a counter being updated between two consecutive reads on RTIUC1 and RTIFRC1.
A read of this register will return the value of the counter when the RTIFRC1 was read.
A write to this register presets the counter. The counter then increments from this written value
upwards.
Note: If counters must be preset, they must be disabled in the RTIGCTRL register to
ensure consistency between RTIUC1 and RTIFRC1.
Note: If the preset value is bigger than the compare value stored in register RTICPUC1,
then it can take a long time until a compare matches, since RTIUC1 has to count up until
it overflows.
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