RTI Control Registers
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SPNU563A–March 2018
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Real-Time Interrupt (RTI) Module
17.3.12 RTI Compare Up Counter 1 Register (RTICPUC1)
The compare up counter 1 register holds the value compared with prescale counter 1. This register is
shown in Figure 17-23 and described in Table 17-13.
Figure 17-23. RTI Compare Up Counter 1 Register (RTICPUC1) [offset = 38h]
31 16
CPUC1
R/WP-0
15 0
CPUC1
R/WP-0
LEGEND: R/W = Read/Write; WP = Write in privileged mode only; -n = value after reset
Table 17-13. RTI Compare Up Counter 1 Register (RTICPUC1) Field Descriptions
Bit Field Value Description
31-0 CPUC1 0-FFFF FFFFh Compare up counter 1. This register holds the compare value, which is compared with the up
counter 1. When the compare matches, the free running counter 1 (RTIFRC1) is incremented.
The up counter is cleared to 0 when the counter value matches the CPUC1 value. The value
set in this prescales the RTI clock according to the following formula:
If CPUC1 = 0, then
f
FRC1
= RTICLK/(2
32
+1) (Setting CPUC1 equal to 0 is not recommended. Doing so will hold the
Up Counter at 0 for 2 RTICLK cycles after it overflows from FFFF FFFFh to 0.)
If CPUC1 ≠ 0, then
f
FRC1
= RTICLK/(RTICPUC1+1)
A read of this register returns the current compare value.
A write to this register updates the compare value.
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