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RTI Control Registers
605
SPNU563A–March 2018
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Real-Time Interrupt (RTI) Module
17.3.13 RTI Capture Free Running Counter 1 Register (RTICAFRC1)
The capture free running counter 1 register holds the current value of free running counter 1 on external
events. This register is shown in Figure 17-24 and described in Table 17-14.
Figure 17-24. RTI Capture Free Running Counter 1 Register (RTICAFRC1) [offset = 40h]
31 16
CAFRC1
R-0
15 0
CAFRC1
R-0
LEGEND: R = Read only; -n = value after reset
Table 17-14. RTI Capture Free Running Counter 1 Register (RTICAFRC1) Field Descriptions
Bit Field Value Description
31-0 CAFRC1 0-FFFF FFFFh Capture free running counter 1. This register captures the current value of the free running
counter 1 (RTIFRC1) when an event occurs, controlled by the external capture control block.
A read of this register returns the value of RTIFRC1 on a capture event.
17.3.14 RTI Capture Up Counter 1 Register (RTICAUC1)
The capture up counter 1 register holds the current value of prescale counter 1 on external events. This
register is shown in Figure 17-25 and described in Table 17-15.
Figure 17-25. RTI Capture Up Counter 1 Register (RTICAUC1) [offset = 44h]
31 16
CAUC1
R-0
15 0
CAUC1
R-0
LEGEND: R = Read only; -n = value after reset
Table 17-15. RTI Capture Up Counter 1 Register (RTICAUC1) Field Descriptions
Bit Field Value Description
31-0 CAUC1 0-FFFF FFFFh Capture up counter 1. This register captures the current value of the up counter 1 (RTIUC1)
when an event occurs, controlled by the external capture control block.
Note: The RTICAFRC1 register must be read before the RTICAUC1 register is read. This
sequence ensures that the value of the RTICAUC1 register is the corresponding value to
the RTICAFRC1 register, even if another capture event happens in between the two
reads.
A read of this register returns the value of RTIUC1 on a capture event.
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