RTI Control Registers
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SPNU563A–March 2018
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Real-Time Interrupt (RTI) Module
17.3.38 RTI Compare 2 Clear Register (RTICMP2CLR)
This registers holds an initial value which is larger than the value in the RTI Compare 2 register
Section 17.3.4. The user needs to choose the value such that the compare clear 2 event occurs before
next compare 2 event. If the Free Running Counter matches the compare value, the compare 2 interrupt
request flag is cleared and the value in the RTIUDCP2 register Section 17.3.20 is added to this register.
This register is shown in Figure 17-49 and described in Table 17-40.
Figure 17-49. RTI Compare 2 Clear Register (RTICMP2CLR) [offset = B8h]
31 16
CMP2CLR
R/WP-0
15 0
CMP2CLR
R/WP-0
LEGEND: R/W = Read/Write; WP = Write in privileged mode only; -n = value after reset
Table 17-40. RTI Compare 2 Clear Register (RTICMP2CLR) Field Descriptions
Bit Field Value Description
31-0 CMP2CLR 0-FFFF FFFFh Compare 2 clear. This registers holds a compare value. If the Free Running Counter matches
the compare value, the compare 2 interrupt request flag is cleared and the value in the
RTIUDCP2 register Section 17.3.20 is added to this register.
Reads return the current compare clear value.
A privileged write to this register updates the compare clear value.
17.3.39 RTI Compare 3 Clear Register (RTICMP3CLR)
This registers holds an initial value which is larger than the value in the RTI Compare 3 register
Section 17.3.4. The user needs to choose the value such that the compare clear 3 event occurs before
next compare 3 event. If the Free Running Counter matches the compare value, the compare 3 interrupt
request flag is cleared and the value in the RTIUDCP3 register Section 17.3.22 is added to this register.
This register is shown in Figure 17-50 and described in Table 17-41.
Figure 17-50. RTI Compare 3 Clear Register (RTICMP3CLR) [offset = BCh]
31 16
CMP3CLR
R/WP-0
15 0
CMP3CLR
R/WP-0
LEGEND: R/W = Read/Write; WP = Write in privileged mode only; -n = value after reset
Table 17-41. RTI Compare 3 Clear Register (RTICMP3CLR) Field Descriptions
Bit Field Value Description
31-0 CMP3CLR 0-FFFF FFFFh Compare 3 clear. This registers holds a compare value. If the Free Running Counter matches
the compare value, the compare 3 interrupt request flag is cleared and the value in the
RTIUDCP3 register Section 17.3.22 is added to this register.
Reads return the current compare clear value.
A privileged write to this register updates the compare clear value.
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