Texas Instruments TMS570LC4357 User Manual

www.ti.com RTI Control Registers
623
SPNU563A–March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated
Real-Time Interrupt (RTI) Module
17.3.36 RTI Compare 0 Clear Register (RTICMP0CLR)
This registers holds an initial value which is larger than the value in the RTI Compare 0 register
Section 17.3.4. The user needs to choose the value such that the compare clear 0 event occurs before
next compare 0 event. If the Free Running Counter matches the compare value, the compare 0 interrupt
request flag is cleared and the value in the RTIUDCP0 register Section 17.3.16 is added to this register.
This register is shown in Figure 17-47 and described in Table 17-38.
Figure 17-47. RTI Compare 0 Clear Register (RTICMP0CLR) [offset = B0h]
31 16
CMP0CLR
R/WP-0
15 0
CMP0CLR
R/WP-0
LEGEND: R/W = Read/Write; WP = Write in privileged mode only; -n = value after reset
Table 17-38. RTI Compare 0 Clear Register (RTICMP0CLR) Field Descriptions
Bit Field Value Description
31-0 CMP0CLR 0-FFFF FFFFh Compare 0 clear. This registers holds a compare value. If the Free Running Counter matches
the compare value, the compare 0 interrupt request flag is cleared and the value in the
RTIUDCP0 register Section 17.3.16 is added to this register.
Reads return the current compare clear value.
A privileged write to this register updates the compare clear value.
17.3.37 RTI Compare 1 Clear Register (RTICMP1CLR)
This registers holds an initial value which is larger than the value in the RTI Compare 1 register
Section 17.3.4. The user needs to choose the value such that the compare clear 1 event occurs before
next compare 1 event. If the Free Running Counter matches the compare value, the compare 1 interrupt
request flag is cleared and the value in the RTIUDCP1 register Section 17.3.18 is added to this register.
This register is shown in Figure 17-48 and described in Table 17-39.
Figure 17-48. RTI Compare 1 Clear Register (RTICMP1CLR) [offset = B4h]
31 16
CMP1CLR
R/WP-0
15 0
CMP1CLR
R/WP-0
LEGEND: R/W = Read/Write; WP = Write in privileged mode only; -n = value after reset
Table 17-39. RTI Compare 1 Clear Register (RTICMP1CLR) Field Descriptions
Bit Field Value Description
31-0 CMP0CLR 0-FFFF FFFFh Compare 1 clear. This registers holds a compare value. If the Free Running Counter matches
the compare value, the compare 1 interrupt request flag is cleared and the value in the
RTIUDCP1 register Section 17.3.18 is added to this register.
Reads return the current compare clear value.
A privileged write to this register updates the compare clear value.

Texas Instruments TMS570LC4357 Specifications

General

Brand	Texas Instruments
Model	TMS570LC4357
Category	Microcontrollers
Language	English