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RTI Control Registers
611
SPNU563A–March 2018
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Real-Time Interrupt (RTI) Module
17.3.25 RTI Set Interrupt Enable Register (RTISETINTENA)
This register prevents the necessity of a read-modify-write operation if a particular interrupt should be
enabled. This register is shown in Figure 17-36 and described in Table 17-26.
Figure 17-36. RTI Set Interrupt Control Register (RTISETINTENA) [offset = 80h]
31 24
Reserved
R-0
23 19 18 17 16
Reserved SETOVL1INT SETOVL0INT SETTBINT
R-0 R/WP-0 R/WP-0 R/WP-0
15 12 11 10 9 8
Reserved SETDMA3 SETDMA2 SETDMA1 SETDMA0
R-0 R/WP-0 R/WP-0 R/WP-0 R/WP-0
7 4 3 2 1 0
Reserved SETINT3 SETINT2 SETINT1 SETINT0
R-0 R/WP-0 R/WP-0 R/WP-0 R/WP-0
LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset
Table 17-26. RTI Set Interrupt Control Register (RTISETINTENA) Field Descriptions
Bit Field Value Description
31-19 Reserved 0 Reads return 0. Writes have no effect.
18 SETOVL1INT Set free running counter 1 overflow interrupt.
0 Read: Interrupt is disabled.
Write: Corresponding bit is unchanged.
1 Read or Write: Interrupt is enabled.
17 SETOVL0INT Set free running counter 0 overflow interrupt.
0 Read: Interrupt is disabled.
Write: Corresponding bit is unchanged.
1 Read or Write: Interrupt is enabled.
16 SETTBINT Set timebase interrupt.
0 Read: Interrupt is disabled.
Write: Corresponding bit is unchanged.
1 Read or Write: Interrupt is enabled.
15-12 Reserved 0 Reads return 0. Writes have no effect.
11 SETDMA3 Set compare DMA request 3.
0 Read: DMA request is disabled.
Write: DMA request is unchanged.
1 Read or Write: DMA request is enabled.
10 SETDMA2 Set compare DMA request 2.
0 Read: DMA request is disabled.
Write: DMA request is unchanged.
1 Read or Write: DMA request is enabled.
9 SETDMA1 Set compare DMA request 1.
0 Read: DMA request is disabled.
Write: DMA request is unchanged.
1 Read or Write: DMA request is enabled.
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