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RTI Control Registers

613

SPNU563A–March 2018

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Real-Time Interrupt (RTI) Module

17.3.26 RTI Clear Interrupt Enable Register (RTICLEARINTENA)

This register prevents the necessity of a read-modify-write operation if a particular interrupt should be

disabled. This register is shown in Figure 17-37 and described in Table 17-27.

Figure 17-37. RTI Clear Interrupt Control Register (RTICLEARINTENA) [offset = 84h]

31 24

Reserved

R-0

23 19 18 17 16

Reserved CLEAROVL1INT CLEAROVL0INT CLEARTBINT

R-0 R/WP-0 R/WP-0 R/WP-0

15 12 11 10 9 8

Reserved CLEARDMA3 CLEARDMA2 CLEARDMA1 CLEARDMA0

R-0 R/WP-0 R/WP-0 R/WP-0 R/WP-0

7 4 3 2 1 0

Reserved CLEARINT3 CLEARINT2 CLEARINT1 CLEARINT0

R-0 R/WP-0 R/WP-0 R/WP-0 R/WP-0

LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset

Table 17-27. RTI Clear Interrupt Control Register (RTICLEARINTENA) Field Descriptions

Bit Field Value Description

31-19 Reserved 0 Reads return 0. Writes have no effect.

18 CLEAROVL1INT Clear free running counter 1 overflow interrupt.

0 Read: Interrupt is disabled.