RTI Control Registers
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SPNU563A–March 2018
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Real-Time Interrupt (RTI) Module
17.3.30 Watchdog Status Register (RTIWDSTATUS)
This register records the status of the DWD. The values of the following status bits will not be affected by
a soft reset. These bits are cleared by a power-on reset, or by a write of 1. These bits can be used for
debug purposes. This register is shown in Figure 17-38 and described in Table 17-28.
Figure 17-41. Watchdog Status Register (RTIWDSTATUS) [offset = 98h]
31 8
Reserved
R-0
7 6 5 4 3 2 1 0
Reserved DWWD ST END TIME VIOL START TIME VIOL KEY ST DWD ST Reserved
R-0 R/W1CP-x R/W1CP-x R/W1CP-x R/W1CP-x R/W1CP-x R-0
LEGEND: R/W = Read/Write; R = Read only; W1CP = Write 1 to clear in privilege mode only; -n = value after reset
Table 17-31. Watchdog Status Register (RTIWDSTATUS) Field Descriptions
Bit Field Value Description
31-6 Reserved 0 Reads return 0. Writes have no effect.
5 DWWD ST Windowed Watchdog Status
0 Read: No time-window violation has occurred.
Write: Leaves the current value unchanged.
1 Read: Time-window violation has occurred. The watchdog has generated either a system reset
or a non-maskable interrupt to the CPU in this case.
Write: Bit is cleared to 0. This will also clear all other status flags in the RTIWDSTATUS
register. Clearing of the status flags will deassert the non-maskable interrupt generated due to
violation of the DWWD.
4 END TIME VIOL Windowed Watchdog End Time Violation Status.
This bit indicates whether the Watchdog counter expired.
0 Read: No end-time window violation has occurred.
Write: Leaves the current value unchanged.
1 Read: End-time defined by the windowed watchdog configuration has been violated.
Write: Bit is cleared to 0.
3 START TIME VIOL Windowed Watchdog Start Time Violation Status.
This bit indicates whether the key is written before the watchdog window opened up.
0 Read: No start-time window violation has occurred.
Write: Leaves the current value unchanged.
1 Read: Start-time defined by the windowed watchdog configuration has been violated.
Write: Bit is cleared to 0.
2 KEY ST Watchdog key status. This bit indicates a reset or NMI generated by a wrong key or key
sequence written to the RTIWDKEY register.
0 Read: No wrong key or key-sequence written.
Write: Bit is unchanged.
1 Read: Wrong key or key-sequence written to RTIWDKEY register.
Write: Bit is cleared to 0.
1 DWD ST DWD status.
This bit is equivalent to bit END TIME VIOL.
0 Read: No reset or NMI was generated.
Write: Bit is unchanged.
1 Read: Reset or NMI was generated.
Write: Bit is cleared to 0.
0 Reserved 0 Reads return 0. Writes have no effect.
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