Texas Instruments TMS570LC4357

STC1 Segment 0 (CPU) Test Coverage and Duration www.ti.com
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SPNU563A–March 2018
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Self-Test Controller (STC) Module
Table 10-2. STC1 Segment 0 Test Coverage and Duration (continued)
Intervals Test Coverage (%) Test Time (Cycles)
44 90.57 71676
45 90.67 73305
46 90.77 74934
47 90.89 76563
48 91.00 78192
49 91.08 79821
50 91.17 81450
51 91.26 83079
52 91.35 84708
53 91.42 86337
54 91.52 87966
55 91.63 89595
56 91.73 91224
57 91.81 92853
58 91.89 94482
59 91.97 96111
60 92.05 97740
61 92.11 99369
62 92.17 100998
63 92.24 102627
64 92.31 104256
65 92.38 105885
66 92.44 107514
67 92.51 109143
68 92.57 110772
69 92.63 112401
70 92.70 114030
71 92.76 115659
72 92.82 117288
73 92.92 118917
74 92.98 120546
75 93.06 122175
76 93.12 123804
77 93.20 125433
78 93.25 127062
79 93.31 128691
80 93.36 130320
81 93.42 131949
82 93.48 133578
83 93.55 135207
84 93.60 136836
85 93.66 138465
86 93.71 140094
87 93.76 141723
88 93.81 143352
89 93.86 144981
90 93.91 146610