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679
SPNU563A–March 2018
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Vectored Interrupt Manager (VIM) Module
Example 19-4 shows a fast response to the FIQ interrupt in Index Interrupt and can be applied to a system
that has more than one channel assigned as a FIQ. It is built in Index Interrupt compatible with
TMS470R1x legacy code.
Example 19-4. How to Respond to FIQ With Short Latency
.sect ".intvecs" ; Interrupt and exception vector sector
00000000h b _RESET ; RESET interrupt
00000004h b _UNDEF_INST_INT ; UNDEFINED INSTRUCTION interrupt
00000008h b _SW_INT ; SOFTWARE interrupt
0000000Ch b _ABORT_PREF_INT ; ABORT (PREFETCH) interrupt
00000010h b _ABORT_DATA_INT ; ABORT (DATA) interrupt
00000014h b #-8 ; Reserved
00000018h b _IRQ_ENTRY_0 ; IRQ interrupt
;*********************************
; INTERRUPT PROCESSING AREA
;*********************************
0000001Ch ldrb R8, [PC,#-0x21d] ; FIQ INTERRUPT ENTRY
; R8 used to get the FIQ index
; with address pointer to the
; first FIQ banked register
00000020h ldr PC, [PC, R8, LSL#2] ; Branch to the indexed interrupt
; routine. The prefetch
; operation causes the PC to be 2
; words (8 bytes) ahead of the
; current instruction, so
; pointing to _INT_TABLE.
00000024h nop ; Required due to pipeline.
;=================================
00000028h _INT_TABLE ; FIQ INTERRUPT DISPATCH
;=================================
0000002Ch .word _FIQ_TABLE ; beginning of FIQ Dispatch
00000030h .word _ISR1 ; dispatch to interrupt routine 1
00000034h .word _ISR2 ; dispatch to interrupt routine 2
.
.
Another way to improve the FIQ latency is to assign only one channel to the FIQ interrupt and to map the
ISR code corresponding to this channel directly starting at 0x1C.
NOTE: When the CPU is in vector-enabled mode, Example 19-3 and Example 19-4 are still valid.
The difference is that the CPU will not read from the 0x18 location during IRQ interrupt, but
will jump directly to the corresponding ISR routine.
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