Control Registers and Control Packets
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SPNU563A–March 2018
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Direct Memory Access Controller (DMA) Module
20.3.1.35 BTC Interrupt Enable Set Register (BTCINTENAS)
Figure 20-53. BTC Interrupt Enable Set Register (BTCINTENAS) [offset = 10Ch]
31 0
BTCINTENA[31:0]
R/WP-0
LEGEND: R/W = Read/Write; WP = Write in privilege mode only; -n = value after reset
Table 20-43. BTC Interrupt Enable Reset Register (BTCINTENAS) Field Descriptions
Bit Field Value Description
31-0 BTCINTENA[n] Block transfer complete (BTC) interrupt enable. Bit 0 corresponds to channel 0, bit 1 corresponds to
channel 1, and so on.
0 Read: BTC interrupt of the corresponding channel is disabled.
Write: No effect.
1 Read and write: BTC interrupt of the corresponding channel is enabled.
20.3.1.36 BTC Interrupt Enable Reset Register (BTCINTENAR)
Figure 20-54. BTC Interrupt Enable Reset Register (BTCINTENAR) [offset = 114h]
31 0
BTCINTDIS[31:0]
R/WP-0
LEGEND: R/W = Read/Write; WP = Write in privilege mode only; -n = value after reset
Table 20-44. BTC Interrupt Enable Reset Register (BTCINTENAR) Field Descriptions
Bit Field Value Description
31-0 BTCINTDIS[n] Block transfer complete (BTC) interrupt disable. Bit 0 corresponds to channel 0, bit 1 corresponds
to channel 1, and so on.
0 Read: BTC interrupt of the corresponding channel is disabled.
Write: No effect.
1 Read: BTC interrupt of the corresponding channel is enabled.
Write: BTC interrupt of the corresponding channel is disabled.
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