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Control Registers and Control Packets
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SPNU563A–March 2018
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Direct Memory Access Controller (DMA) Module
20.3.1.33 HBC Interrupt Enable Set Register (HBCINTENAS)
Figure 20-51. HBC Interrupt Enable Set Register (HBCINTENAS) [offset = FCh]
31 0
HBCINTENA[31:0]
R/WP-0
LEGEND: R/W = Read/Write; WP = Write in privilege mode only; -n = value after reset
Table 20-41. HBC Interrupt Enable Set Register (HBCINTENAS) Field Descriptions
Bit Field Value Description
31-0 HBCINTENA[n] Half block complete (HBC) interrupt enable. Bit 0 corresponds to channel 0, bit 1 corresponds to
channel 1, and so on.
0 Read: HBC interrupt of the corresponding channel is disabled.
Write: No effect.
1 Read and write: HBC interrupt of the corresponding channel is enabled.
20.3.1.34 HBC Interrupt Enable Reset Register (HBCINTENAR)
Figure 20-52. HBC Interrupt Enable Reset Register (HBCINTENAR) [offset = 104h]
31 0
HBCINTDIS[31:0]
R/WP-0
LEGEND: R/W = Read/Write; WP = Write in privilege mode only; -n = value after reset
Table 20-42. HBC Interrupt Enable Reset Register (HBCINTENAR) Field Descriptions
Bit Field Value Description
31-0 HBCINTDIS[n] Half block complete (HBC) interrupt disable. Bit 0 corresponds to channel 0, bit 1 corresponds to
channel 1, and so on.
0 Read: HBC interrupt of the corresponding channel is disabled.
Write: No effect.
1 Read: HBC interrupt of the corresponding channel is enabled.
Write: HBC interrupt of the corresponding channel is disabled.
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