Texas Instruments TMS570LC4357 User Manual

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SPNU563A–March 2018
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Direct Memory Access Controller (DMA) Module
Table 20-7. DMA Control Registers (continued)
Offset Acronym Register Description Section
230h DMAECCSBE DMA ECC Single-bit Error Address Register Section 20.3.1.85
240h FIFOASTATREG FIFO A Status Register Section 20.3.1.86
244h FIFOBSTATREG FIFO B Status Register Section 20.3.1.87
330h DMAREQPS1 DMA Request Polarity Select Register 1 Section 20.3.1.88
334h DMAREQPS0 DMA Request Polarity Select Register 0 Section 20.3.1.89
340h TERECTRL TER Event Control Register Section 20.3.1.90
344h TERFLAG TER Event Flag Register Section 20.3.1.91
348h TERROFFSET TER Event Channel Offset Register Section 20.3.1.92
Table 20-8. Control Packet Memory Map
Offset Acronym Register Description Section
Primary Control Packet 0
00h ISADDR Initial Source Address Register Section 20.3.2.1
04h IDADDR Initial Destination Address Register Section 20.3.2.2
08h ITCOUNT Initial Transfer Count Register Section 20.3.2.3
10h CHCTRL Channel Control Register Section 20.3.2.4
14h EIOFF Element Index Offset Register Section 20.3.2.5
18h FIOFF Frame Index Offset Register Section 20.3.2.6
Working Control Packet 0
800h CSADDR Current Source Address Register Section 20.3.2.7
804h CDADDR Current Destination Address Register Section 20.3.2.8
808h CTCOUNT Current Transfer Count Register Section 20.3.2.9

Texas Instruments TMS570LC4357 Specifications

General

Brand	Texas Instruments
Model	TMS570LC4357
Category	Microcontrollers
Language	English