Control Registers and Control Packets
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SPNU563A–March 2018
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Direct Memory Access Controller (DMA) Module
20.3.1.86 FIFO A Status Register (FIFOASTAT)
Figure 20-103. FIFO A Status Register (FIFOASTAT) [offset = 240h]
31 0
FFACH[31:0]
R-0
LEGEND: R = Read only; -n = value after reset
Table 20-93. FIFO A Status Register (FIFOASTAT) Field Descriptions
Bit Field Value Description
31-0 FFACH[n] Status of DMA channel running using FIFO A. Bit 0 corresponds to channel 0, bit 1 corresponds to
channel 1, and so on.
0 The channel is not being currently processed.
1 The channel is currently being processed using FIFO A.
Note: The status of a channel currently being processed remains active, even if emulation mode is
entered or DMA is disabled by way of the DMA_EN bit. Up to 1 bit can be set in this register at any
given time.
20.3.1.87 FIFO B Status Register (FIFOBSTAT)
Figure 20-104. FIFO B Status Register (FIFOBSTAT) [offset = 244h]
31 0
FFBCH[31:0]
R-0
LEGEND: R = Read only; -n = value after reset
Table 20-94. FIFO B Status Register (FIFOBSTAT) Field Descriptions
Bit Field Value Description
31-0 FFBCH[n] Status of DMA channel running using FIFO B. Bit 0 corresponds to channel 0, bit 1 corresponds to
channel 1, and so on.
0 The channel is not being currently processed.
1 The channel is currently being processed using FIFO B.
Note: The status of a channel currently being processed remains active, even if emulation mode is
entered or DMA is disabled by way of the DMA_EN bit. Up to 1 bit can be set in this register at any
given time.
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