Control Registers and Control Packets
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SPNU563A–March 2018
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Direct Memory Access Controller (DMA) Module
20.3.1.90 Transaction Parity Error Event Control Register (TERECTRL)
Figure 20-107. Transaction Parity Error Event Control Register (TERECTRL) [offset = 340h]
31 17 16
Reserved TER_ERR
R-0 R/W1C-0
15 4 3 0
Reserved TER_EN
R-0 R/WP-Ah
LEGEND: R/W = Read/Write; R = Read only; W1C = Write 1 to clear; WP = Write in privilege mode only; -n = value after reset
Table 20-97. Transaction Parity Error Event Control Register (TERECTRL) Field Descriptions
Bit Field Value Description
31-17 Reserved 0 Reads return 0. Writes have no effect.
16 TER_ERR Transactions parity error status.
0 Read: No error occurred.
Write: No effect.
1 Read: A transaction error has occurred
Write: Clears the bit.
15-4 Reserved 0 Reads return 0. Writes have no effect.
3-0 TER_EN Transaction error event detection enable.
5h Write: Disable transaction error event detection by DMA .
Read: Transaction error event will not be detected by DMA.
Ah Write: Enable transaction error event detection by DMA.
Read: Transaction error event will be detected by DMA.
20.3.1.91 TER Event Flag Register (TERFLAG)
Figure 20-108. TER Event Flag Register (TERFLAG) [offset = 344h]
31 0
TERE[31:0]
R/W1CP-0
LEGEND: R/W = Read/Write; W1CP = Write 1 to clear in privilege mode only; -n = value after reset
Table 20-98. TER Event Flag Register (TERFLAG) Field Descriptions
Bit Field Value Description
31-0 TERE[n] If the bit is set, a TER event of the corresponding channel is pending. Bit 0 corresponds to channel
0, bit 1 corresponds to channel 1, and so on.
0 Read: The associated TER Event of a channel is NOT pending.
Write: No effect.
1 Read: The associated TER Event of a channel is pending.
Write: Clear this bit.
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