Control Registers and Control Packets
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SPNU563A–March 2018
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Direct Memory Access Controller (DMA) Module
20.3.2.7 Current Source Address Register (CSADDR)
Figure 20-116. Current Source Address Register (CSADDR) [offset = 800h]
31 0
CSADDR
R-X
LEGEND: R = Read only; X = value is unknown; -n = value after reset
Table 20-106. Current Source Address Register (CSADDR) Field Descriptions
Bit Field Description
31-0 CSADDR Current source address. These bits contain the current working absolute 32-bit source address (physical).
These bits are only updated after a channel is arbitrated out from the priority queue.
20.3.2.8 Current Destination Address Register (CDADDR)
Figure 20-117. Current Destination Address Register (CDADDR) [offset = 804h]
31 0
CDADDR
R-X
LEGEND: R = Read only; X = value is unknown; -n = value after reset
Table 20-107. Current Destination Address Register (CDADDR) Field Descriptions
Bit Field Description
31-0 CDADDR Current destination address. These bits contain the current working absolute 32-bit destination address
(physical). These bits are only updated after a channel is arbitrated out of the priority queue.
20.3.2.9 Current Transfer Count Register (CTCOUNT)
Figure 20-118. Current Transfer Count Register (CTCOUNT) [offset = 808h]
31 29 28 16
Reserved CFTCOUNT
R-X R-X
15 13 12 0
Reserved CETCOUNT
R-X R-X
LEGEND: R = Read only; X = value is unknown; -n = value after reset
Table 20-108. Current Transfer Count Register (CTCOUNT) Field Descriptions
Bit Field Value Description
31-29 Reserved 0 Reads are undefined. Writes have no effect.
28-16 CFTCOUNT 0-1FFFh Current frame transfer count. Returned the current remaining frame counts.
15-13 Reserved 0 Reads are undefined. Writes have no effect.
12-0 CETCOUNT 0-1FFFh Current element transfer count. These bits return the current remaining element counts.
CTCOUNT register is only updated after a channel is arbitrated out of the priority queue.