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Control Registers and Control Packets
733
SPNU563A–March 2018
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Direct Memory Access Controller (DMA) Module
20.3.1.15 DMA Request Assignment Register 2 (DREQASI2)
Figure 20-33. DMA Request Assignment Register 2 (DREQASI2) [offset = 5Ch]
31 30 29 24 23 22 21 16
Reserved CH8ASI Reserved CH9ASI
R-0 R/WP-8h R-0 R/WP-9h
15 14 13 8 7 6 5 0
Reserved CH10ASI Reserved CH11ASI
R-0 R/WP-Ah R-0 R/WP-Bh
LEGEND: R/W = Read/Write; R = Read only; WP = Write in privilege mode only; -n = value after reset
Table 20-23. DMA Request Assignment Register 2 (DREQASI2) Field Descriptions
Bit Field Value Description
31-30 Reserved 0 Reads return 0. Writes have no effect.
29-24 CH8ASI Channel 8 assignment. This bit field chooses the DMA request assignment for channel 8.
0 DMA request line 0 triggers channel 8.
: :
2Fh DMA request line 47 triggers channel 8.
30h-
3Fh
Reserved
23-22 Reserved 0 Reads return 0. Writes have no effect.
21-16 CH9ASI Channel 9 assignment. This bit field chooses the DMA request assignment for channel 9.
0 DMA request line 0 triggers channel 9.
: :
2Fh DMA request line 47 triggers channel 9.
30h-
3Fh
Reserved
15-14 Reserved 0 Reads return 0. Writes have no effect.
13-8 CH10ASI Channel 10 assignment. This bit field chooses the DMA request assignment for channel 10.
0 DMA request line 0 triggers channel 10.
: :
2Fh DMA request line 47 triggers channel 10.
30h-
3Fh
Reserved
7-6 Reserved 0 Reads return 0. Writes have no effect.
5-0 CH11ASI Channel 11 assignment. This bit field chooses the DMA request assignment for channel 11.
0 DMA request line 0 triggers channel 11.
: :
2Fh DMA request line 47 triggers channel 11.
30h-
3Fh
Reserved
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