Control Registers and Control Packets
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SPNU563A–March 2018
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Direct Memory Access Controller (DMA) Module
20.3.1.14 DMA Request Assignment Register 1 (DREQASI1)
Figure 20-32. DMA Request Assignment Register 1 (DREQASI1) [offset = 58h]
31 30 29 24 23 22 21 16
Reserved CH4ASI Reserved CH5ASI
R-0 R/WP-4h R-0 R/WP-5h
15 14 13 8 7 6 5 0
Reserved CH6ASI Reserved CH7ASI
R-0 R/WP-6h R-0 R/WP-7h
LEGEND: R/W = Read/Write; R = Read only; WP = Write in privilege mode only; -n = value after reset
Table 20-22. DMA Request Assignment Register 1 (DREQASI1) Field Descriptions
Bit Field Value Description
31-30 Reserved 0 Reads return 0. Writes have no effect.
29-24 CH4ASI Channel 4 assignment. This bit field chooses the DMA request assignment for channel 4.
0 DMA request line 0 triggers channel 4.
: :
2Fh DMA request line 47 triggers channel 4.
30h-
3Fh
Reserved
23-22 Reserved 0 Reads return 0. Writes have no effect.
21-26 CH5ASI Channel 5 assignment. This bit field chooses the DMA request assignment for channel 5.
0 DMA request line 0 triggers channel 5.
: :
2Fh DMA request line 47 triggers channel 5.
30h-
3Fh
Reserved
15-14 Reserved 0 Reads return 0. Writes have no effect.
13-8 CH6ASI Channel 6 assignment. This bit field chooses the DMA request assignment for channel 6.
0 DMA request line 0 triggers channel 6.
: :
2Fh DMA request line 47 triggers channel 6.
30h-
3Fh
Reserved
7-6 Reserved 0 Reads return 0. Writes have no effect.
5-0 CH7ASI Channel 7 assignment. This bit field chooses the DMA request assignment for channel 7.
0 DMA request line 0 triggers channel 7.
: :
2Fh DMA request line 47 triggers channel 7.
30h-
3Fh
Reserved
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