Control Registers and Control Packets
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SPNU563A–March 2018
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Direct Memory Access Controller (DMA) Module
20.3.1.16 DMA Request Assignment Register 3 (DREQASI3)
Figure 20-34. DMA Request Assignment Register 3 (DREQASI3) [offset = 60h]
31 30 29 24 23 22 21 16
Reserved CH12ASI Reserved CH13ASI
R-0 R/WP-Ch R-0 R/WP-Dh
15 14 13 8 7 6 5 0
Reserved CH14ASI Reserved CH15ASI
R-0 R/WP-Eh R-0 R/WP-Fh
LEGEND: R/W = Read/Write; R = Read only; WP = Write in privilege mode only; -n = value after reset
Table 20-24. DMA Request Assignment Register 3 (DREQASI3) Field Descriptions
Bit Field Value Description
31-30 Reserved 0 Reads return 0. Writes have no effect.
29-24 CH12ASI Channel 12 assignment. This bit field chooses the DMA request assignment for channel 12.
0 DMA request line 0 triggers channel 12.
: :
2Fh DMA request line 47 triggers channel 12.
30h-
3Fh
Reserved
23-22 Reserved 0 Reads return 0. Writes have no effect.
21-16 CH13ASI Channel 13 assignment. This bit field chooses the DMA request assignment for channel 13.
0 DMA request line 0 triggers channel 13.
: :
2Fh DMA request line 47 triggers channel 13.
30h-
3Fh
Reserved
15-14 Reserved 0 Reads return 0. Writes have no effect.
13-8 CH14ASI Channel 14 assignment. This bit field chooses the DMA request assignment for channel 14.
0 DMA request line 0 triggers channel 14.
: :
2Fh DMA request line 47 triggers channel 14.
30h-
3Fh
Reserved
7-6 Reserved 0 Reads return 0. Writes have no effect.
5-0 CH15ASI Channel 15 assignment. This bit field chooses the DMA request assignment for channel 15.
0 DMA request line 0 triggers channel 15.
: :
2Fh DMA request line 47 triggers channel 15.
30h-
3Fh
Reserved
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