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Control Registers and Control Packets
745
SPNU563A–March 2018
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Direct Memory Access Controller (DMA) Module
20.3.1.29 FTC Interrupt Enable Set Register (FTCINTENAS)
Figure 20-47. FTC Interrupt Enable Set Register (FTCINTENAS) [offset = DCh]
31 0
FTCINTENA[31:0]
R/WP-0
LEGEND: R/W = Read/Write; WP = Write in privilege mode only; -n = value after reset
Table 20-37. FTC Interrupt Enable Set Register (FTCINTENAS) Field Descriptions
Bit Field Value Description
31-0 FTCINTENA[n] Frame transfer complete (FTC) interrupt enable. Bit 0 corresponds to channel 0, bit 1 corresponds
to channel 1, and so on.
0 Read: Corresponding FTC interrupt of a channel is disabled.
Write: No effect.
1 Read and write: FTC interrupt of the corresponding channel is enabled.
20.3.1.30 FTC Interrupt Enable Reset Register (FTCINTENAR)
Figure 20-48. FTC Interrupt Enable Reset (FTCINTENAR) [offset = E4h]
31 0
FTCINTDIS[31:0]
R/WP-0
LEGEND: R/W = Read/Write; WP = Write in privilege mode only; -n = value after reset
Table 20-38. FTC Interrupt Enable Reset (FTCINTENAR) Field Descriptions
Bit Field Value Description
31-0 FTCINTDIS[n] Frame transfer complete (FTC) interrupt disable. Bit 0 corresponds to channel 0, bit 1 corresponds
to channel 1, and so on.
0 Read: Corresponding FTC interrupt of a channel is disabled.
Write: No effect.
1 Read: Corresponding FTC interrupt of a channel is enabled.
Write: Corresponding FTC interrupt is disabled.
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