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System and Peripheral Control Registers
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SPNU563A–March 2018
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Architecture
2.5.3.32 Peripheral Frame n MasterID Protection Register_L/H (PS[1-31]MSTID_L/H)
There is one bit for each quadrant for PS0 to PS31. The protection scheme is described in
Section 2.5.3.30. This register is shown in Figure 2-103 and described in Table 2-117.
Figure 2-103. Peripheral Frame n MasterID Protection Register_L/H (PSnMSTID_L/H)
(offset = 308h-3FCh)
31 16
PSn_QUAD3_MSTID or PSn_QUAD1_MSTID
R/WP-FFFFh
15 0
PSn_QUAD2_MSTID or PSn_QUAD0_MSTID
R/WP-FFFFh
LEGEND: R/W = Read/Write; WP = Write in privileged mode only; -n = value after reset
Table 2-117. Peripheral Frame n MasterID Protection Register_L/H (PSnMSTID_L/H)
Field Descriptions
Bit Field Value Description
31-16 PSn_QUAD3_MSTID or
PSn_QUAD1_MSTID
n: 1 to 31. L: quadrant0 and quadrant1. H: quadrant2 and quadrant3.
MasterID filtering for Quadrant 3 of PS[n] or Quadrant 1 of PS[n].
0 Read: The corresponding master-ID is not permitted to access the peripheral.
Write: Disable the permission of the corresponding master to access the peripheral.
1 Read: The corresponding master-ID is permitted to access the peripheral.
Write: Enable the permission of the corresponding master to access the peripheral.
15-0 PSn_QUAD2_MSTID or
PSn_QUAD0_MSTID
MasterID filtering for Quadrant 2 of PS[n] or Quadrant 0 of PS[n].
0 Read: The corresponding master-ID is not permitted to access the peripheral.
Write: Disable the permission of the corresponding master to access the peripheral.
1 Read: The corresponding master-ID is permitted to access the peripheral.
Write: Enable the permission of the corresponding master to access the peripheral.
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