System and Peripheral Control Registers
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SPNU563A–March 2018
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Architecture
2.5.3.31 Peripheral Frame 0 MasterID Protection Register_H (PS0MSTID_H)
There is one bit for each quadrant for PS0 to PS31. The protection scheme is described in
Section 2.5.3.30. This register is shown in Figure 2-102 and described in Table 2-116.
Figure 2-102. Peripheral Frame 0 MasterID Protection Register_H (PS0MSTID_H)
(offset = 304h)
31 16
PS0_QUAD3_MSTID
R/WP-FFFFh
15 0
PS0_QUAD2_MSTID
R/WP-FFFFh
LEGEND: R/W = Read/Write; WP = Write in privileged mode only; -n = value after reset
Table 2-116. Peripheral Frame 0 MasterID Protection Register_H (PS0MSTID_H)
Field Descriptions
Bit Field Value Description
31-16 PS0_QUAD3_MSTID MasterID filtering for Quadrant 3 of PS[0].
0 Read: The corresponding master-ID is not permitted to access the peripheral.
Write: Disable the permission of the corresponding master to access the peripheral.
1 Read: The corresponding master-ID is permitted to access the peripheral.
Write: Enable the permission of the corresponding master to access the peripheral.
15-0 PS0_QUAD2_MSTID MasterID filtering for Quadrant 2 of PS[0].
0 Read: The corresponding master-ID is not permitted to access the peripheral.
Write: Disable the permission of the corresponding master to access the peripheral.
1 Read: The corresponding master-ID is permitted to access the peripheral.
Write: Enable the permission of the corresponding master to access the peripheral.
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