System and Peripheral Control Registers
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SPNU563A–March 2018
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Architecture
2.5.3.13 Peripheral Memory Power-Down Set Register 0 (PCSPWRDWNSET0)
Each bit corresponds to a bit at the same index in the PMPROT register in that they both relate to the
same peripheral. This register is shown in Figure 2-84 and described in Table 2-98.
NOTE: Only those bits that have a slave at the corresponding bit position are implemented. Writes
to unimplemented bits have no effect and reads are 0.
Figure 2-84. Peripheral Memory Power-Down Set Register 0 (PCSPWRDWNSET0) (offset = 60h)
31 0
PCS[31-0]PWRDNSET
R/WP-1
LEGEND: R/W = Read/Write; WP = Write in privileged mode only; -n = value after reset
Table 2-98. Peripheral Memory Power-Down Set Register 0 (PCSPWRDWNSET0) Field Descriptions
Bit Field Value Description
31-0 PCS[31-0]PWRDNSET Peripheral memory clock power-down set.
0 Read: The peripheral memory clock[31-0] is active.
Write: The bit is unchanged.
1 Read: The peripheral memory clock[31-0] is inactive.
Write: The corresponding bit in the PCSPWRDWNSET0 and PCSPWRDWNCLR0 registers
is set to 1.
2.5.3.14 Peripheral Memory Power-Down Set Register 1 (PCSPWRDWNSET1)
This register is shown in Figure 2-85 and described in Table 2-99.
NOTE: Only those bits that have a slave at the corresponding bit position are implemented. Writes
to unimplemented bits have no effect and reads are 0.
Figure 2-85. Peripheral Memory Power-Down Set Register 1 (PCSPWRDWNSET1) (offset = 64h)
31 0
PCS[63-32]PWRDNSET
R/WP-1
LEGEND: R/W = Read/Write; WP = Write in privileged mode only; -n = value after reset
Table 2-99. Peripheral Memory Power-Down Set Register 1 (PCSPWRDWNSET1) Field Descriptions
Bit Field Value Description
31-0 PCS[63-32]PWRDNSET Peripheral memory clock power-down set.
0 Read: The peripheral memory clock[63-32] is active.
Write: The bit is unchanged.
1 Read: The peripheral memory clock[63-32] is inactive.
Write: The corresponding bit in the PCSPWRDWNSET1 and PCSPWRDWNCLR1 registers
is set to 1.
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