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System and Peripheral Control Registers
231
SPNU563A–March 2018
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Architecture
2.5.3.15 Peripheral Memory Power-Down Clear Register 0 (PCSPWRDWNCLR0)
This register is shown in Figure 2-86 and described in Table 2-100.
NOTE: Only those bits that have a slave at the corresponding bit position are implemented. Writes
to unimplemented bits have no effect and reads are 0.
Figure 2-86. Peripheral Memory Power-Down Clear Register 0 (PCSPWRDWNCLR0)
(offset = 70h)
31 0
PCS[31-0]PWRDNCLR
R/WP-1
LEGEND: R/W = Read/Write; WP = Write in privileged mode only; -n = value after reset
Table 2-100. Peripheral Memory Power-Down Clear Register 0 (PCSPWRDWNCLR0)
Field Descriptions
Bit Field Value Description
31-0 PCS[31-0]PWRDNCLR Peripheral memory clock power-down clear.
0 Read: The peripheral memory clock[31-0] is active.
Write: The bit is unchanged.
1 Read: The peripheral memory clock[31-0] is inactive.
Write: The corresponding bit in the PCSPWRDWNSET0 and PCSPWRDWNCLR0 registers
is cleared to 0.
2.5.3.16 Peripheral Memory Power-Down Clear Register 1 (PCSPWRDWNCLR1)
This register is shown in Figure 2-87 and described in Table 2-101.
NOTE: Only those bits that have a slave at the corresponding bit position are implemented. Writes
to unimplemented bits have no effect and reads are 0.
Figure 2-87. Peripheral Memory Power-Down Clear Register 1 (PCSPWRDWNCLR1)
(offset = 74h)
31 0
PCS[63-32]PWRDNCLR
R/WP-1
LEGEND: R/W = Read/Write; WP = Write in privileged mode only; -n = value after reset
Table 2-101. Peripheral Memory Power-Down Set Register 1 (PCSPWRDWNCLR1)
Field Descriptions
Bit Field Value Description
31-0 PCS[63-32]PWRDNCLR Peripheral memory clock power-down clear.
0 Read: The peripheral memory clock[63-32] is active.
Write: The bit is unchanged.
1 Read: The peripheral memory clock[63-32] is inactive.
Write: The corresponding bit in the PCSPWRDWNSET1 and PCSPWRDWNCLR1 registers
is cleared to 0.
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