System and Peripheral Control Registers
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SPNU563A–March 2018
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Architecture
2.5.3.17 Peripheral Power-Down Set Register 0 (PSPWRDWNSET0)
There is one bit for each quadrant for PS0 to PS7. Each bit of this register corresponds to the bit at the
same index in the corresponding PPROT register in that they relate to the same peripheral. These bits are
used to power down/power up the clock to the corresponding peripheral.
For every bit implemented in the PPROT register, there is one bit in the PSnPWRDWN register, except
when two peripherals (both in PS area) share buses. In that case, only one Power-Down bit is
implemented, at the position corresponding to that peripheral whose quadrant comes first (the lower
numbered).
The ways in which quadrants can be used within a frame are identical to what is described under
PPROTSET0, Section 2.5.3.5.
This arrangement is the same for bits of PS8 to PS31, presented in Section 2.5.3.18 - Section 2.5.3.24.
This register holds bits for PS0 to PS7. This register is shown in Figure 2-88 and described in Table 2-
102.
NOTE: Only those bits that have a slave at the corresponding bit position are implemented. Writes
to unimplemented bits have no effect and reads are 0.
Figure 2-88. Peripheral Power-Down Set Register 0 (PSPWRDWNSET0) (offset = 80h)
31 0
PS[7-0]QUAD[3-0]PWRDWNSET
R/WP-1
LEGEND: R/W = Read/Write; WP = Write in privileged mode only; -n = value after reset
Table 2-102. Peripheral Power-Down Set Register 0 (PSPWRDWNSET0) Field Descriptions
Bit Field Value Description
31-0 PS[7-0]QUAD[3-0]
PWRDWNSET
Peripheral select quadrant clock power-down set.
0 Read: The clock to the peripheral select quadrant is active.
Write: The bit is unchanged.
1 Read: The clock to the peripheral select quadrant is inactive.
Write: The corresponding bit in PSPWRDWNSET0 and PSPWRDWNCLR0 registers is set
to 1.
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