Texas Instruments TMS570LC4357 User Manual

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SPNU563A–March 2018
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Architecture
2.5.3.22 Peripheral Power-Down Clear Register 1 (PSPWRDWNCLR1)
There is one bit for each quadrant for PS8 to PS15. The protection scheme is described in
Section 2.5.3.17. This register is shown in Figure 2-93 and described in Table 2-107.
NOTE: Only those bits that have a slave at the corresponding bit position are implemented. Writes
to unimplemented bits have no effect and reads are 0.
Figure 2-93. Peripheral Power-Down Clear Register 1 (PSPWRDWNCLR1) (offset = A4h)
31 0
PS[15-8]QUAD[3-0]PWRDWNCLR
R/WP-1
LEGEND: R/W = Read/Write; WP = Write in privileged mode only; -n = value after reset
Table 2-107. Peripheral Power-Down Clear Register 1 (PSPWRDWNCLR1) Field Descriptions
Bit Field Value Description
31-0 PS[15-8]QUAD[3-0]
PWRDWNCLR
Peripheral select quadrant clock power-down clear.
0 Read: The clock to the peripheral select quadrant is active.
Write: The bit is unchanged.
1 Read: The clock to the peripheral select quadrant is inactive.
Write: The corresponding bit in PSPWRDWNSET1 and PSPWRDWNCLR1 registers is
cleared to 0.
2.5.3.23 Peripheral Power-Down Clear Register 2 (PSPWRDWNCLR2)
There is one bit for each quadrant for PS16 to PS23. The protection scheme is described in
Section 2.5.3.17. This register is shown in Figure 2-94 and described in Table 2-108.
NOTE: Only those bits that have a slave at the corresponding bit position are implemented. Writes
to unimplemented bits have no effect and reads are 0.
Figure 2-94. Peripheral Power-Down Clear Register 2 (PSPWRDWNCLR2) (offset = A8h)
31 0
PS[23-16]QUAD[3-0]PWRDWNCLR
R/WP-1
LEGEND: R/W = Read/Write; WP = Write in privileged mode only; -n = value after reset
Table 2-108. Peripheral Power-Down Clear Register 2 (PSPWRDWNCLR2) Field Descriptions
Bit Field Value Description
31-0 PS[23-16]QUAD[3-0]
PWRDWNCLR
Peripheral select quadrant clock power-down clear.
0 Read: The clock to the peripheral select quadrant is active.
Write: The bit is unchanged.
1 Read: The clock to the peripheral select quadrant is inactive.
Write: The corresponding bit in PSPWRDWNSET2 and PSPWRDWNCLR2 registers is
cleared to 0.

Texas Instruments TMS570LC4357 Specifications

General

Brand	Texas Instruments
Model	TMS570LC4357
Category	Microcontrollers
Language	English