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System and Peripheral Control Registers
223
SPNU563A–March 2018
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Architecture
2.5.3.1 Peripheral Memory Protection Set Register 0 (PMPROTSET0)
This register is shown in Figure 2-72 and described in Table 2-86.
NOTE: Only those bits that have a slave at the corresponding bit position are implemented. Writes
to non-implemented bits have no effect and reads are 0.
Figure 2-72. Peripheral Memory Protection Set Register 0 (PMPROTSET0) (offset = 00h)
31 0
PCS[31-0]PROTSET
R/WP-0
LEGEND: R/W = Read/Write; WP = Write in privileged mode only; -n = value after reset
Table 2-86. Peripheral Memory Protection Set Register 0 (PMPROTSET0) Field Descriptions
Bit Field Value Description
31-0 PCS[31-0]PROTSET Peripheral memory frame protection set.
0 Read: The peripheral memory framen can be written to and read from in both user and
privileged modes.
Write: The bit is unchanged.
1 Read: The peripheral memory framen can be written to only in privileged mode, but it can be
read in both user and privileged modes.
Write: The corresponding bit in PMPROTSET0 and PMPROTCLR0 registers is set to 1.
2.5.3.2 Peripheral Memory Protection Set Register 1 (PMPROTSET1)
This register is shown in Figure 2-73 and described in Table 2-87.
NOTE: Only those bits that have a slave at the corresponding bit position are implemented. Writes
to unimplemented bits have no effect and reads are 0.
Figure 2-73. Peripheral Memory Protection Set Register 1 (PMPROTSET1) (offset = 04h)
31 0
PCS[63-32]PROTSET
R/WP-0
LEGEND: R/W = Read/Write; WP = Write in privileged mode only; -n = value after reset
Table 2-87. Peripheral Memory Protection Set Register 1 (PMPROTSET1) Field Descriptions
Bit Field Value Description
31-0 PCS[63-32]PROTSET Peripheral memory frame protection set.
0 Read: The peripheral memory framen can be written to and read from in both user and
privileged modes.
Write: The bit is unchanged.
1 Read: The peripheral memory framen can be written to only in privileged mode, but it can be
read in both user and privileged modes.
Write: The corresponding bit in PMPROTSET1 and PMPROTCLR1 registers is set to 1.