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System and Peripheral Control Registers
237
SPNU563A–March 2018
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Architecture
2.5.3.26 Debug Frame Powerdown Clear Register (PDPWRDWNCLR)
Figure 2-97. Debug Frame Powerdown Clear Register (PDPWRDWNCLR) (offset = C4h)
31 1 0
Reserved PDWRDWNCLR
R-0 R/WP-1
LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset
Table 2-111. Debug Frame Powerdown Clear Register (PDPWRDWNCLR) Field Descriptions
Bit Field Value Description
31-1 Reserved 0 Reads return 0. Writes have no effect.
0 PDWRDWNCLR Debug Frame Powerdown Set Register.
0 Read: The clock to the debug frame is active.
Write: The bit is unchanged.
1 Read: The clock to the debug frame is inactive.
Write: Clear the bit to 0.
2.5.3.27 MasterID Protection Write Enable Register (MSTIDWRENA)
Figure 2-98. MasterID Protection Write Enable Register (MSTIDWRENA) (offset = 200h)
31 16
Reserved
R-0
15 4 3 0
Reserved MSTIDREG_WRENA
R-0 R/WP-5h
LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset
Table 2-112. MasterID Protection Write Enable Register (MSTIDWRENA) Field Descriptions
Bit Field Value Description
31-4 Reserved 0 Reads return 0. Writes have no effect.
3-0 MSTIDREG_WRENA MasterID Register Write Enable. This is a 4-bit key for enabling writes to all Master-ID
registers from address offset 0x300-0x5DC. This key must be programmed with 1010 to
unlock writes to all Master-ID registers.
Ah Read: All master-ID registers are unlocked and available for writes.
Write: Writes to master-ID registers are unlocked.
Others Read: Writes to all master-ID registers are locked.
Write: Write to master-ID registers are locked.
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