I2C Operation Modes
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SPNU563A–March 2018
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Inter-Integrated Circuit (I2C) Module
31.3 I2C Operation Modes
31.3.1 Master Transmitter Mode
All masters begin in this mode. The I2C module is a master and transmits control information and data to
a slave. In this mode, data assembled in any of the addressing formats shown in Figure 31-7, Figure 31-8,
or Figure 31-9 is shifted out onto the SDA pin and synchronized with the self-generated clock pulses on
the SCL pin. The clock pulses are inhibited and the SCL pin is held low when the intervention of the
device is required (XSMT = 0) after a byte has been transmitted.
NOTE: If the I2C is configured for two simultaneous master transmissions, wait until the MST and
BB have been reset before performing the second master transmission.
Failure to wait for the MST and BB to reset will prevent the start condition on the second transfer from
being issued and the bus BB will not be set. Typically the end of the first transfer is handled by polling BB.
However, the MST bit is not reset at the same instant as the BB bit. As a result, when the second master
transmission is initiated before the resetting of the MST, the MST bit for the second transfer is reset. This
prevents the I2C from recognizing itself as the master, thus failing to occupy the bus.
31.3.2 Master Receiver Mode
In this mode, the I2C module is a master and receives data from a slave. This mode can only be entered
from the master transmitter mode (the I2C module must first transmit a command to the slave). In any of
the addressing formats shown in Figure 31-7, Figure 31-8, or Figure 31-9, the master receiver mode is
entered after the slave address byte and the R/W bit have been transmitted (if the R/W bit is 1). Serial
data bits received on the SDA pin are shifted in with the self-generated clock pulses on the SCL pin. The
clock pulses are inhibited and the SCL is held low when the intervention of the device is required
(RSFULL = 1) after a byte has been received. At the end of the transfer, the master-receiver signals the
end of data to the slave-transmitter by not generating an acknowledge on the last byte that was clocked
out of the slave. The slave-transmitter then releases the data line allowing the master-receiver to generate
a STOP condition or a repeated START condition.
In many applications, the size of the message is in the initial bytes of the message itself. Since the size of
the message is not known to the master before the transmission/reception starts, the master must use the
repeat mode in order to force the stop condition when the reception is completed. The repeat mode is
enabled by setting the RM bit to 1. Due to the double buffer implementation on the receive side, the
master must generate the stop condition (STP =1) after reading the (message size - 1)
th
data.
31.3.3 Slave Transmitter Mode
In this mode, the I2C module is a slave and transmits data to a master. This mode can only be entered
from the slave receiver mode (The I2C module must first receive a command from the master). In any of
the addressing formats shown in Figure 31-7, Figure 31-8, or Figure 31-9, the slave transmitter mode is
entered if the slave address byte is the same as its own address and the R/W bit has been transmitted (if
the R/W bit is set to 1). The slave transmitter shifts the serial data out on the SDA pin with the clock
pulses that are generated by the master device. The slave device does not generate the clock, but it can
hold the SCL pin low when intervention of the device is required (XSMT = 0) after a byte has been
transmitted.
31.3.4 Slave Receiver Mode
In this mode, the I2C module is a slave and receives data from a master. All slaves begin in this mode.
Serial data bits received on the SDA pin are shifted in with the clock pulses that are generated by the
master device. The slave device does not generate the clock, but it can hold the SCL pin low while
intervention of the device is required (RSFULL = 1) after a byte has been received.
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