2.115256
2
20045.0
]0...8[ =´
´
=M U LM O D
2
20045.0
2256
]0...8[ ´
=
´
==D
NSNVM U LM O D
NF
2
2 0
9 021 0 0
5.0
´=´==
N VN S
N F
N V
D e pth
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Programming Example
541
SPNU563A–March 2018
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Copyright © 2018, Texas Instruments Incorporated
Oscillator and PLL
5. Compute the divider value NV:
(18)
NV = 0.045
6. If it is important to maintain the same average frequency in modulation as in non-modulation, either NF
should be modified OR program the MULMOD bit field. The modulation fields create a multiplier offset
equal to:
(19)
If using MULMOD[8:0], then:
(20)
(21)
MULMOD will be set to 115.
7. Convert the PLL parameters into bit field values:
• NR = 5, implies that REFCLKDIV[5:0] = 4
• NS = 20, implies that SPRATE[8:0] = 19 = 0x13
• NF = 90, implies that PLLMUL[15:0] = 0x5900
• OD = 2, implies that ODPLL[2:0] = 1
• R = 1, implies that PLLDIV[4:0] = 0
• NV = 0.045, implies that SPR_AMOUNT[8:0] = 91 = 0x5B
• MULMOD[8:0] = 115 = 0x73
8. Setting only these fields (that is, not BPOS, ROF, or ROS) yields:
PLLCTL1 = 0x00045900
PLLCTL2 = 0x04C7325B
When FM ENA is turned on, PLLCTL2 = 0x84C7325B.
The Output CLK is centered in the range from 150 MHz to 550 MHz at 360 MHz.
NF = 90 falls within the multiplier range from 1 to 256.
OD is selected so that post-ODCLK meets the device specification.
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