TC1796
System Units (Vol. 1 of 2)
Register Overview
User’s Manual 18-54 V2.0, 2007-07
Regs, V2.0
DMA_
ME1PR
DMA Move Engine 1
Pattern Register
F000 3C40
H
U, SV SV 0000 0000
H
DMA_
ME0AENR
DMA Move Engine 0
Access Enable Register
F000 3C44
H
U, SV SV, E 0000 0000
H
DMA_
ME0ARR
DMA Move Engine 0
Access Range Register
F000 3C48
H
U, SV SV, E 0000 0000
H
DMA_
ME1AENR
DMA Move Engine 1
Access Enable Register
F000 3C4C
H
U, SV SV, E 0000 0000
H
DMA_
ME1ARR
DMA Move Engine 1
Access Range Register
F000 3C50
H
U, SV SV, E 0000 0000
H
DMA_
INTSR
DMA Interrupt Status
Register
F000 3C54
H
U, SV BE 0000 0000
H
DMA_
INTCR
DMA Interrupt Clear
Register
F000 3C58
H
U, SV SV 0000 0000
H
DMA_
WRPSR
DMA Wrap Status
Register
F000 3C5C
H
U, SV BE 0000 0000
H
– Reserved F000 3C60
H
BE BE –
DMA_
OCDSR
DMA OCDS Register F000 3C64
H
U, SV SV, E 0000 0000
H
DMA_
SUSPMR
DMA Suspend Mode
Register
F000 3C68
H
U, SV SV, E 0000 0000
H
– Reserved F000 3C6C
H
-
F000 3C7C
H
BE BE –
DMA_
CHSR00
DMA Channel 00 Status
Register
F000 3C80
H
U, SV BE 0000 0000
H
DMA_
CHCR00
DMA Channel 00 Control
Register
F000 3C84
H
U, SV SV 0000 0000
H
DMA_
CHICR00
DMA Channel 00
Interrupt Control Register
F000 3C88
H
U, SV SV 0000 0000
H
DMA_
ADRCR00
DMA Channel 00
Address Control Register
F000 3C8C
H
U, SV SV 0000 0000
H
DMA_
SADR00
DMA Channel 00 Source
Address Register
F000 3C90
H
U, SV SV 0000 0000
H
Table 18-23 Address Map of DMA (cont’d)
Short Name Description Address Access Mode Reset Value
Read Write
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