TC1796
System Units (Vol. 1 of 2)
Register Overview
User’s Manual 18-55 V2.0, 2007-07
Regs, V2.0
DMA_
DADR00
DMA Channel 00
Destination Address
Reg.
F000 3C94
H
U, SV SV 0000 0000
H
DMA_
SHADR00
DMA Channel 00
Shadow Address
Register
F000 3C98
H
U, SV BE 0000 0000
H
– Reserved F000 3C9C
H
BE BE –
DMA_
CHSR01
DMA Channel 01 Status
Register
F000 3CA0
H
U, SV BE 0000 0000
H
DMA_
CHCR01
DMA Channel 01 Control
Register
F000 3CA4
H
U, SV SV 0000 0000
H
DMA_
CHICR01
DMA Channel 01
Interrupt Control Register
F000 3CA8
H
U, SV SV 0000 0000
H
DMA_
ADRCR01
DMA Channel 01Address
Control Register
F000 3CAC
H
U, SV SV 0000 0000
H
DMA_
SADR01
DMA Channel 01 Source
Address Register
F000 3CB0
H
U, SV SV 0000 0000
H
DMA_
DADR01
DMA Channel 01
Destination Address
Reg.
F000 3CB4
H
U, SV SV 0000 0000
H
DMA_
SHADR01
DMA Channel 01
Shadow Address
Register
F000 3CB8
H
U, SV BE 0000 0000
H
– Reserved F000 3CBC
H
BE BE –
DMA_
CHSR02
DMA Channel 02 Status
Register
F000 3CC0
H
U, SV BE 0000 0000
H
DMA_
CHCR02
DMA Channel 02 Control
Register
F000 3CC4
H
U, SV SV 0000 0000
H
DMA_
CHICR02
DMA Channel 02
Interrupt Control Register
F000 3CC8
H
U, SV SV 0000 0000
H
DMA_
ADRCR02
DMA Channel 02
Address Control Register
F000 3CCC
H
U, SV SV 0000 0000
H
DMA_
SADR02
DMA Channel 02 Source
Address Register
F000 3CD0
H
U, SV SV 0000 0000
H
Table 18-23 Address Map of DMA (cont’d)
Short Name Description Address Access Mode Reset Value
Read Write
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