TC1796
System Units (Vol. 1 of 2)
Register Overview
User’s Manual 18-106 V2.0, 2007-07
Regs, V2.0
– Reserved F7E1 C020
H
-
F7E1 C3FC
H
nE nE –
DPR1_0L Data Seg. Prot. Reg. Set
1, Range 0, Lower
Boundary
F7E1 C400
H
U, SV,
32
SV,
32
0000 0000
H
DPR1_0U Data Seg. Prot. Reg. Set
1, Range 0, Upper
Boundary
F7E1 C404
H
U, SV,
32
SV,
32
0000 0000
H
DPR1_1L Data Seg. Prot. Reg. Set
1, Range 1, Lower
Boundary
F7E1 C408
H
U, SV,
32
SV,
32
0000 0000
H
DPR1_1U Data Seg. Prot. Reg. Set
1, Range 1, Upper
Boundary
F7E1 C40C
H
U, SV,
32
SV,
32
0000 0000
H
DPR1_2L Data Seg. Prot. Reg. Set
1, Range 2, Lower
Boundary
F7E1 C410
H
U, SV,
32
SV,
32
0000 0000
H
DPR1_2U Data Seg. Prot. Reg. Set
1, Range 2, Upper
Boundary
F7E1 C414
H
U, SV,
32
SV,
32
0000 0000
H
DPR1_3L Data Seg. Prot. Reg. Set
1, Range 3, Lower
Boundary
F7E1 C418
H
U, SV,
32
SV,
32
0000 0000
H
DPR1_3U Data Seg. Prot. Reg. Set
1, Range 3, Upper
Boundary
F7E1 C41C
H
U, SV,
32
SV,
32
0000 0000
H
– Reserved F7E1 C420
H
-
F7E1 CFFC
H
nE nE –
CPR0_0L Code Seg. Prot. Reg. Set
0, Rng. 0, Lower
Boundary
F7E1 D000
H
U, SV,
32
SV,
32
0000 0000
H
CPR0_0U Code Seg. Prot. Reg. Set
0, Rng. 0, Upper
Boundary
F7E1 D004
H
U, SV,
32
SV,
32
0000 0000
H
Table 18-33 Address Map of CPU Core SFRs & GPRs (cont’d)
Short
Name
Description Address Access Mode Reset Value
Read Write