Infineon Technologies TC1796 - Page 1096

TC1796
System Units (Vol. 1 of 2)
Register Overview
User’s Manual 18-107 V2.0, 2007-07
Regs, V2.0
CPR0_1L Code Seg. Prot. Reg. Set
0, Rng. 1, Lower
Boundary
F7E1 D008
H
U, SV,
32
SV,
32
0000 0000
H
CPR0_1U Code Seg. Prot. Reg. Set
0, Rng. 1, Upper
Boundary
F7E1 D00C
H
U, SV,
32
SV,
32
0000 0000
H
– Reserved F7E1 D010
H
-
F7E1 D3FC
H
nE nE –
CPR1_0L Code Seg. Prot. Reg. Set
1, Rng. 0, Lower
Boundary
F7E1 D400
H
U, SV,
32
SV,
32
0000 0000
H
CPR1_0U Code Seg. Prot. Reg. Set
1, Rng. 0, Upper
Boundary
F7E1 D404
H
U, SV,
32
SV,
32
0000 0000
H
CPR1_1L Code Seg. Prot. Reg. Set
1, Rng. 1, Lower
Boundary
F7E1 D408
H
U, SV,
32
SV,
32
0000 0000
H
CPR1_1U Code Seg. Prot. Reg. Set
1, Rng. 1, Upper
Boundary
F7E1 D40C
H
U, SV,
32
SV,
32
0000 0000
H
– Reserved F7E1 D410
H
-
F7E1 DFFC
H
nE nE –
DPM0 Data Protection Mode
Register Set 0
F7E1 E000
H
U, SV,
32
SV,
32
0000 0000
H
– Reserved F7E1 E004
H
-
F7E1 E07C
H
nE nE –
DPM1 Data Protection Mode
Register Set 1
F7E1 E080
H
U, SV,
32
SV,
32
0000 0000
H
– Reserved F7E1 E084
H
-
F7E1 E1FC
H
nE nE –
CPM0 Code Protection Mode
Register Set 0
F7E1 E200
H
U, SV,
32
SV,
32
0000 0000
H
– Reserved F7E1 E204
H
-
F7E1 E27C
H
nE nE –
Table 18-33 Address Map of CPU Core SFRs & GPRs (cont’d)
Short
Name
Description Address Access Mode Reset Value
Read Write