Infineon Technologies TC1796 - Page 1108

TC1796
System Units (Vol. 1 of 2)
Register Overview
User’s Manual 18-119 V2.0, 2007-07
Regs, V2.0
DMU_
OTAR3
DMU Overlay Target
Address Register 3
F801 0148
H
U, SV SV 0000 0000
H
DMU_
OMASK3
DMU Overlay Mask
Register 3
F801 014C
H
U, SV SV 0FFF FE00
H
DMU_
RABR4
DMU Redirected Address
Base Register 4
F801 0150
H
U, SV SV 0000 0000
H
DMU_
OTAR4
DMU Overlay Target
Address Register 4
F801 0154
H
U, SV SV 0000 0000
H
DMU_
OMASK4
DMU Overlay Mask
Register 4
F801 0158
H
U, SV SV 0FFF FE00
H
DMU_
RABR5
DMU Redirected Address
Base Register 5
F801 015C
H
U, SV SV 0000 0000
H
DMU_
OTAR5
DMU Overlay Target
Address Register 5
F801 0160
H
U, SV SV 0000 0000
H
DMU_
OMASK5
DMU Overlay Mask
Register 5
F801 0164
H
U, SV SV 0FFF FE00
H
DMU_
RABR6
DMU Redirected Address
Base Register 6
F801 0168
H
U, SV SV 0000 0000
H
DMU_
OTAR6
DMU Overlay Target
Address Register 6
F801 016C
H
U, SV SV 0000 0000
H
DMU_
OMASK6
DMU Overlay Mask
Register 6
F801 0170
H
U, SV SV 0FFF FE00
H
DMU_
RABR7
DMU Redirected Address
Base Register 7
F801 0174
H
U, SV SV 0000 0000
H
DMU_
OTAR7
DMU Overlay Target
Address Register 7
F801 0178
H
U, SV SV 0000 0000
H
DMU_
OMASK7
DMU Overlay Mask
Register 7
F801 017C
H
U, SV SV 0FFF FE00
H
DMU_
RABR8
DMU Redirected Address
Base Register 8
F801 0180
H
U, SV SV 0000 0000
H
DMU_
OTAR8
DMU Overlay Target
Address Register 8
F801 0184
H
U, SV SV 0000 0000
H
Table 18-37 Address Map of DMU (cont’d)
Short Name Description Address Access Mode Reset Value
Read Write